Path: blob/master/sound/soc/mediatek/mt8192/mt8192-interconnection.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* Mediatek MT8192 audio driver interconnection definition3*4* Copyright (c) 2020 MediaTek Inc.5* Author: Shane Chien <[email protected]>6*/78#ifndef _MT8192_INTERCONNECTION_H_9#define _MT8192_INTERCONNECTION_H_1011/* in port define */12#define I_I2S0_CH1 013#define I_I2S0_CH2 114#define I_ADDA_UL_CH1 315#define I_ADDA_UL_CH2 416#define I_DL1_CH1 517#define I_DL1_CH2 618#define I_DL2_CH1 719#define I_DL2_CH2 820#define I_PCM_1_CAP_CH1 921#define I_GAIN1_OUT_CH1 1022#define I_GAIN1_OUT_CH2 1123#define I_GAIN2_OUT_CH1 1224#define I_GAIN2_OUT_CH2 1325#define I_PCM_2_CAP_CH1 1426#define I_ADDA_UL_CH3 1727#define I_ADDA_UL_CH4 1828#define I_DL12_CH1 1929#define I_DL12_CH2 2030#define I_PCM_2_CAP_CH2 2131#define I_PCM_1_CAP_CH2 2232#define I_DL3_CH1 2333#define I_DL3_CH2 2434#define I_I2S2_CH1 2535#define I_I2S2_CH2 2636#define I_I2S2_CH3 2737#define I_I2S2_CH4 283839/* in port define >= 32 */40#define I_32_OFFSET 3241#define I_CONNSYS_I2S_CH1 (34 - I_32_OFFSET)42#define I_CONNSYS_I2S_CH2 (35 - I_32_OFFSET)43#define I_SRC_1_OUT_CH1 (36 - I_32_OFFSET)44#define I_SRC_1_OUT_CH2 (37 - I_32_OFFSET)45#define I_SRC_2_OUT_CH1 (38 - I_32_OFFSET)46#define I_SRC_2_OUT_CH2 (39 - I_32_OFFSET)47#define I_DL4_CH1 (40 - I_32_OFFSET)48#define I_DL4_CH2 (41 - I_32_OFFSET)49#define I_DL5_CH1 (42 - I_32_OFFSET)50#define I_DL5_CH2 (43 - I_32_OFFSET)51#define I_DL6_CH1 (44 - I_32_OFFSET)52#define I_DL6_CH2 (45 - I_32_OFFSET)53#define I_DL7_CH1 (46 - I_32_OFFSET)54#define I_DL7_CH2 (47 - I_32_OFFSET)55#define I_DL8_CH1 (48 - I_32_OFFSET)56#define I_DL8_CH2 (49 - I_32_OFFSET)57#define I_DL9_CH1 (50 - I_32_OFFSET)58#define I_DL9_CH2 (51 - I_32_OFFSET)59#define I_I2S6_CH1 (52 - I_32_OFFSET)60#define I_I2S6_CH2 (53 - I_32_OFFSET)61#define I_I2S8_CH1 (54 - I_32_OFFSET)62#define I_I2S8_CH2 (55 - I_32_OFFSET)6364#endif656667