Path: blob/master/sound/soc/mediatek/mt8195/mt8195-audsys-clkid.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition3*4* Copyright (c) 2021 MediaTek Inc.5* Author: Trevor Wu <[email protected]>6*/78#ifndef _MT8195_AUDSYS_CLKID_H_9#define _MT8195_AUDSYS_CLKID_H_1011enum{12CLK_AUD_AFE,13CLK_AUD_LRCK_CNT,14CLK_AUD_SPDIFIN_TUNER_APLL,15CLK_AUD_SPDIFIN_TUNER_DBG,16CLK_AUD_UL_TML,17CLK_AUD_APLL1_TUNER,18CLK_AUD_APLL2_TUNER,19CLK_AUD_TOP0_SPDF,20CLK_AUD_APLL,21CLK_AUD_APLL2,22CLK_AUD_DAC,23CLK_AUD_DAC_PREDIS,24CLK_AUD_TML,25CLK_AUD_ADC,26CLK_AUD_DAC_HIRES,27CLK_AUD_A1SYS_HP,28CLK_AUD_AFE_DMIC1,29CLK_AUD_AFE_DMIC2,30CLK_AUD_AFE_DMIC3,31CLK_AUD_AFE_DMIC4,32CLK_AUD_AFE_26M_DMIC_TM,33CLK_AUD_UL_TML_HIRES,34CLK_AUD_ADC_HIRES,35CLK_AUD_ADDA6_ADC,36CLK_AUD_ADDA6_ADC_HIRES,37CLK_AUD_LINEIN_TUNER,38CLK_AUD_EARC_TUNER,39CLK_AUD_I2SIN,40CLK_AUD_TDM_IN,41CLK_AUD_I2S_OUT,42CLK_AUD_TDM_OUT,43CLK_AUD_HDMI_OUT,44CLK_AUD_ASRC11,45CLK_AUD_ASRC12,46CLK_AUD_MULTI_IN,47CLK_AUD_INTDIR,48CLK_AUD_A1SYS,49CLK_AUD_A2SYS,50CLK_AUD_PCMIF,51CLK_AUD_A3SYS,52CLK_AUD_A4SYS,53CLK_AUD_MEMIF_UL1,54CLK_AUD_MEMIF_UL2,55CLK_AUD_MEMIF_UL3,56CLK_AUD_MEMIF_UL4,57CLK_AUD_MEMIF_UL5,58CLK_AUD_MEMIF_UL6,59CLK_AUD_MEMIF_UL8,60CLK_AUD_MEMIF_UL9,61CLK_AUD_MEMIF_UL10,62CLK_AUD_MEMIF_DL2,63CLK_AUD_MEMIF_DL3,64CLK_AUD_MEMIF_DL6,65CLK_AUD_MEMIF_DL7,66CLK_AUD_MEMIF_DL8,67CLK_AUD_MEMIF_DL10,68CLK_AUD_MEMIF_DL11,69CLK_AUD_GASRC0,70CLK_AUD_GASRC1,71CLK_AUD_GASRC2,72CLK_AUD_GASRC3,73CLK_AUD_GASRC4,74CLK_AUD_GASRC5,75CLK_AUD_GASRC6,76CLK_AUD_GASRC7,77CLK_AUD_GASRC8,78CLK_AUD_GASRC9,79CLK_AUD_GASRC10,80CLK_AUD_GASRC11,81CLK_AUD_GASRC12,82CLK_AUD_GASRC13,83CLK_AUD_GASRC14,84CLK_AUD_GASRC15,85CLK_AUD_GASRC16,86CLK_AUD_GASRC17,87CLK_AUD_GASRC18,88CLK_AUD_GASRC19,89CLK_AUD_NR_CLK,90};9192#endif939495