Path: blob/master/sound/soc/mediatek/mt8365/mt8365-afe-clk.h
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/* SPDX-License-Identifier: GPL-2.01*2* MediaTek 8365 AFE clock control definitions3*4* Copyright (c) 2024 MediaTek Inc.5* Authors: Jia Zeng <[email protected]>6* Alexandre Mergnat <[email protected]>7*/89#ifndef _MT8365_AFE_UTILS_H_10#define _MT8365_AFE_UTILS_H_1112struct mtk_base_afe;13struct clk;1415int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe);16void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);17int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, unsigned int rate);18int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, struct clk *parent);19int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);20int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);21int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe);22int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe);23int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe);24int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe);25int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe);26int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe);27int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);28int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);29int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);30int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);31#endif323334