CoCalc -- mt8365-afe-common.h

GitHub Repository: torvalds/linux
Path: blob/master/sound/soc/mediatek/mt8365/mt8365-afe-common.h
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/* SPDX-License-Identifier: GPL-2.0
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 *
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 * MediaTek 8365 audio driver common definitions
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 *
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 * Copyright (c) 2024 MediaTek Inc.
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 * Authors: Jia Zeng <[email protected]>
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 *          Alexandre Mergnat <[email protected]>
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 */
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#ifndef _MT8365_AFE_COMMON_H_
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#define _MT8365_AFE_COMMON_H_
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#include <linux/clk.h>
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#include <linux/list.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include <sound/asound.h>
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#include "../common/mtk-base-afe.h"
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#include "mt8365-reg.h"
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enum {
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	MT8365_AFE_MEMIF_DL1,
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	MT8365_AFE_MEMIF_DL2,
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	MT8365_AFE_MEMIF_TDM_OUT,
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	/*
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	 * MT8365_AFE_MEMIF_SPDIF_OUT,
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	 */
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	MT8365_AFE_MEMIF_AWB,
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	MT8365_AFE_MEMIF_VUL,
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	MT8365_AFE_MEMIF_VUL2,
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	MT8365_AFE_MEMIF_VUL3,
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	MT8365_AFE_MEMIF_TDM_IN,
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	/*
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	 * MT8365_AFE_MEMIF_SPDIF_IN,
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	 */
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	MT8365_AFE_MEMIF_NUM,
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	MT8365_AFE_BACKEND_BASE = MT8365_AFE_MEMIF_NUM,
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	MT8365_AFE_IO_TDM_OUT = MT8365_AFE_BACKEND_BASE,
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	MT8365_AFE_IO_TDM_IN,
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	MT8365_AFE_IO_I2S,
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	MT8365_AFE_IO_2ND_I2S,
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	MT8365_AFE_IO_PCM1,
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	MT8365_AFE_IO_VIRTUAL_DL_SRC,
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	MT8365_AFE_IO_VIRTUAL_TDM_OUT_SRC,
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	MT8365_AFE_IO_VIRTUAL_FM,
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	MT8365_AFE_IO_DMIC,
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	MT8365_AFE_IO_INT_ADDA,
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	MT8365_AFE_IO_GASRC1,
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	MT8365_AFE_IO_GASRC2,
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	MT8365_AFE_IO_TDM_ASRC,
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	MT8365_AFE_IO_HW_GAIN1,
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	MT8365_AFE_IO_HW_GAIN2,
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	MT8365_AFE_BACKEND_END,
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	MT8365_AFE_BACKEND_NUM = (MT8365_AFE_BACKEND_END -
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				  MT8365_AFE_BACKEND_BASE),
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};
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enum {
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	MT8365_AFE_IRQ1,
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	MT8365_AFE_IRQ2,
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	MT8365_AFE_IRQ3,
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	MT8365_AFE_IRQ4,
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	MT8365_AFE_IRQ5,
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	MT8365_AFE_IRQ6,
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	MT8365_AFE_IRQ7,
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	MT8365_AFE_IRQ8,
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	MT8365_AFE_IRQ9,
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	MT8365_AFE_IRQ10,
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	MT8365_AFE_IRQ_NUM,
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};
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enum {
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	MT8365_TOP_CG_AFE,
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	MT8365_TOP_CG_I2S_IN,
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	MT8365_TOP_CG_22M,
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	MT8365_TOP_CG_24M,
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	MT8365_TOP_CG_INTDIR_CK,
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	MT8365_TOP_CG_APLL2_TUNER,
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	MT8365_TOP_CG_APLL_TUNER,
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	MT8365_TOP_CG_SPDIF,
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	MT8365_TOP_CG_TDM_OUT,
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	MT8365_TOP_CG_TDM_IN,
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	MT8365_TOP_CG_ADC,
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	MT8365_TOP_CG_DAC,
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	MT8365_TOP_CG_DAC_PREDIS,
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	MT8365_TOP_CG_TML,
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	MT8365_TOP_CG_I2S1_BCLK,
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	MT8365_TOP_CG_I2S2_BCLK,
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	MT8365_TOP_CG_I2S3_BCLK,
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	MT8365_TOP_CG_I2S4_BCLK,
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	MT8365_TOP_CG_DMIC0_ADC,
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	MT8365_TOP_CG_DMIC1_ADC,
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	MT8365_TOP_CG_DMIC2_ADC,
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	MT8365_TOP_CG_DMIC3_ADC,
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	MT8365_TOP_CG_CONNSYS_I2S_ASRC,
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	MT8365_TOP_CG_GENERAL1_ASRC,
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	MT8365_TOP_CG_GENERAL2_ASRC,
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	MT8365_TOP_CG_TDM_ASRC,
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	MT8365_TOP_CG_NUM
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};
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enum {
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	MT8365_CLK_TOP_AUD_SEL,
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	MT8365_CLK_AUD_I2S0_M,
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	MT8365_CLK_AUD_I2S1_M,
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	MT8365_CLK_AUD_I2S2_M,
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	MT8365_CLK_AUD_I2S3_M,
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	MT8365_CLK_ENGEN1,
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	MT8365_CLK_ENGEN2,
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	MT8365_CLK_AUD1,
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	MT8365_CLK_AUD2,
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	MT8365_CLK_I2S0_M_SEL,
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	MT8365_CLK_I2S1_M_SEL,
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	MT8365_CLK_I2S2_M_SEL,
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	MT8365_CLK_I2S3_M_SEL,
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	MT8365_CLK_CLK26M,
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	MT8365_CLK_NUM
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};
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enum {
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	MT8365_AFE_APLL1 = 0,
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	MT8365_AFE_APLL2,
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	MT8365_AFE_APLL_NUM,
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};
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enum {
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	MT8365_AFE_1ST_I2S = 0,
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	MT8365_AFE_2ND_I2S,
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	MT8365_AFE_I2S_SETS,
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};
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enum {
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	MT8365_AFE_I2S_SEPARATE_CLOCK = 0,
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	MT8365_AFE_I2S_SHARED_CLOCK,
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};
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enum {
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	MT8365_AFE_TDM_OUT_I2S = 0,
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	MT8365_AFE_TDM_OUT_TDM,
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	MT8365_AFE_TDM_OUT_I2S_32BITS,
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};
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enum mt8365_afe_tdm_ch_start {
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	AFE_TDM_CH_START_O28_O29 = 0,
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	AFE_TDM_CH_START_O30_O31,
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	AFE_TDM_CH_START_O32_O33,
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	AFE_TDM_CH_START_O34_O35,
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	AFE_TDM_CH_ZERO,
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};
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enum {
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	MT8365_PCM_FORMAT_I2S = 0,
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	MT8365_PCM_FORMAT_EIAJ,
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	MT8365_PCM_FORMAT_PCMA,
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	MT8365_PCM_FORMAT_PCMB,
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};
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enum {
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	MT8365_FS_8K = 0,
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	MT8365_FS_11D025K,
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	MT8365_FS_12K,
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	MT8365_FS_384K,
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	MT8365_FS_16K,
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	MT8365_FS_22D05K,
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	MT8365_FS_24K,
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	MT8365_FS_130K,
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	MT8365_FS_32K,
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	MT8365_FS_44D1K,
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	MT8365_FS_48K,
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	MT8365_FS_88D2K,
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	MT8365_FS_96K,
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	MT8365_FS_176D4K,
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	MT8365_FS_192K,
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};
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enum {
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	FS_8000HZ  = 0, /* 0000b */
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	FS_11025HZ = 1, /* 0001b */
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	FS_12000HZ = 2, /* 0010b */
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	FS_384000HZ = 3, /* 0011b */
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	FS_16000HZ = 4, /* 0100b */
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	FS_22050HZ = 5, /* 0101b */
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	FS_24000HZ = 6, /* 0110b */
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	FS_130000HZ = 7, /* 0111b */
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	FS_32000HZ = 8, /* 1000b */
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	FS_44100HZ = 9, /* 1001b */
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	FS_48000HZ = 10, /* 1010b */
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	FS_88200HZ = 11, /* 1011b */
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	FS_96000HZ = 12, /* 1100b */
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	FS_176400HZ = 13, /* 1101b */
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	FS_192000HZ = 14, /* 1110b */
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	FS_260000HZ = 15, /* 1111b */
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};
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enum {
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	MT8365_AFE_DEBUGFS_AFE,
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	MT8365_AFE_DEBUGFS_MEMIF,
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	MT8365_AFE_DEBUGFS_IRQ,
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	MT8365_AFE_DEBUGFS_CONN,
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	MT8365_AFE_DEBUGFS_DBG,
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	MT8365_AFE_DEBUGFS_NUM,
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};
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enum {
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	MT8365_AFE_IRQ_DIR_MCU = 0,
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	MT8365_AFE_IRQ_DIR_DSP,
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	MT8365_AFE_IRQ_DIR_BOTH,
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};
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/* MCLK */
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enum {
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	MT8365_I2S0_MCK = 0,
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	MT8365_I2S3_MCK,
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	MT8365_MCK_NUM,
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};
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struct mt8365_fe_dai_data {
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	bool use_sram;
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	unsigned int sram_phy_addr;
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	void __iomem *sram_vir_addr;
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	unsigned int sram_size;
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};
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struct mt8365_be_dai_data {
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	bool prepared[SNDRV_PCM_STREAM_LAST + 1];
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	unsigned int fmt_mode;
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};
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#define MT8365_CLK_26M 26000000
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#define MT8365_CLK_24M 24000000
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#define MT8365_CLK_22M 22000000
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#define MT8365_CM_UPDATA_CNT_SET 8
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enum mt8365_cm_num {
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	MT8365_CM1 = 0,
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	MT8365_CM2,
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	MT8365_CM_NUM,
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};
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enum mt8365_cm2_mux_in {
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	MT8365_FROM_GASRC1 = 1,
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	MT8365_FROM_GASRC2,
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	MT8365_FROM_TDM_ASRC,
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	MT8365_CM_MUX_NUM,
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};
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enum cm2_mux_conn_in {
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	GENERAL2_ASRC_OUT_LCH = 0,
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	GENERAL2_ASRC_OUT_RCH = 1,
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	TDM_IN_CH0 = 2,
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	TDM_IN_CH1 = 3,
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	TDM_IN_CH2 = 4,
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	TDM_IN_CH3 = 5,
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	TDM_IN_CH4 = 6,
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	TDM_IN_CH5 = 7,
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	TDM_IN_CH6 = 8,
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	TDM_IN_CH7 = 9,
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	GENERAL1_ASRC_OUT_LCH = 10,
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	GENERAL1_ASRC_OUT_RCH = 11,
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	TDM_OUT_ASRC_CH0 = 12,
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	TDM_OUT_ASRC_CH1 = 13,
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	TDM_OUT_ASRC_CH2 = 14,
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	TDM_OUT_ASRC_CH3 = 15,
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	TDM_OUT_ASRC_CH4 = 16,
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	TDM_OUT_ASRC_CH5 = 17,
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	TDM_OUT_ASRC_CH6 = 18,
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	TDM_OUT_ASRC_CH7 = 19
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};
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struct mt8365_cm_ctrl_reg {
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	unsigned int con0;
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	unsigned int con1;
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	unsigned int con2;
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	unsigned int con3;
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	unsigned int con4;
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};
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struct mt8365_control_data {
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	bool bypass_cm1;
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	bool bypass_cm2;
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	unsigned int loopback_type;
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};
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enum dmic_input_mode {
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	DMIC_MODE_3P25M = 0,
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	DMIC_MODE_1P625M,
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	DMIC_MODE_812P5K,
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	DMIC_MODE_406P25K,
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};
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enum iir_mode {
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	IIR_MODE0 = 0,
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	IIR_MODE1,
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	IIR_MODE2,
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	IIR_MODE3,
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	IIR_MODE4,
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	IIR_MODE5,
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};
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enum {
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	MT8365_GASRC1 = 0,
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	MT8365_GASRC2,
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	MT8365_GASRC_NUM,
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	MT8365_TDM_ASRC1 = MT8365_GASRC_NUM,
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	MT8365_TDM_ASRC2,
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	MT8365_TDM_ASRC3,
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	MT8365_TDM_ASRC4,
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	MT8365_TDM_ASRC_NUM,
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};
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struct mt8365_gasrc_ctrl_reg {
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	unsigned int con0;
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	unsigned int con2;
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	unsigned int con3;
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	unsigned int con4;
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	unsigned int con5;
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	unsigned int con6;
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	unsigned int con9;
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	unsigned int con10;
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	unsigned int con12;
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	unsigned int con13;
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};
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struct mt8365_gasrc_data {
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	bool duplex;
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	bool tx_mode;
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	bool cali_on;
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	bool tdm_asrc_out_cm2;
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	bool iir_on;
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};
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struct mt8365_afe_private {
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	struct clk *clocks[MT8365_CLK_NUM];
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	struct regmap *topckgen;
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	struct mt8365_fe_dai_data fe_data[MT8365_AFE_MEMIF_NUM];
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	struct mt8365_be_dai_data be_data[MT8365_AFE_BACKEND_NUM];
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	struct mt8365_control_data ctrl_data;
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	struct mt8365_gasrc_data gasrc_data[MT8365_TDM_ASRC_NUM];
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	int afe_on_ref_cnt;
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	int top_cg_ref_cnt[MT8365_TOP_CG_NUM];
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	void __iomem *afe_sram_vir_addr;
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	unsigned int afe_sram_phy_addr;
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	unsigned int afe_sram_size;
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	/* locks */
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	spinlock_t afe_ctrl_lock;
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	struct mutex afe_clk_mutex;	/* Protect & sync APLL TUNER registers access*/
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#ifdef CONFIG_DEBUG_FS
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	struct dentry *debugfs_dentry[MT8365_AFE_DEBUGFS_NUM];
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#endif
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	int apll_tuner_ref_cnt[MT8365_AFE_APLL_NUM];
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	unsigned int tdm_out_mode;
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	unsigned int cm2_mux_input;
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	/* dai */
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	bool dai_on[MT8365_AFE_BACKEND_END];
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	void *dai_priv[MT8365_AFE_BACKEND_END];
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};
358

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static inline u32 rx_frequency_palette(unsigned int fs)
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{
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	/* *
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	 * A = (26M / fs) * 64
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	 * B = 8125 / A
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	 * return = DEC2HEX(B * 2^23)
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	 */
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	switch (fs) {
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	case FS_8000HZ:		return 0x050000;
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	case FS_11025HZ:	return 0x06E400;
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	case FS_12000HZ:	return 0x078000;
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	case FS_16000HZ:	return 0x0A0000;
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	case FS_22050HZ:	return 0x0DC800;
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	case FS_24000HZ:	return 0x0F0000;
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	case FS_32000HZ:	return 0x140000;
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	case FS_44100HZ:	return 0x1B9000;
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	case FS_48000HZ:	return 0x1E0000;
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	case FS_88200HZ:	return 0x372000;
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	case FS_96000HZ:	return 0x3C0000;
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	case FS_176400HZ:	return 0x6E4000;
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	case FS_192000HZ:	return 0x780000;
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	default:		return 0x0;
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	}
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}
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static inline u32 AutoRstThHi(unsigned int fs)
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{
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	switch (fs) {
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	case FS_8000HZ:		return 0x36000;
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	case FS_11025HZ:	return 0x27000;
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	case FS_12000HZ:	return 0x24000;
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	case FS_16000HZ:	return 0x1B000;
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	case FS_22050HZ:	return 0x14000;
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	case FS_24000HZ:	return 0x12000;
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	case FS_32000HZ:	return 0x0D800;
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	case FS_44100HZ:	return 0x09D00;
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	case FS_48000HZ:	return 0x08E00;
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	case FS_88200HZ:	return 0x04E00;
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	case FS_96000HZ:	return 0x04800;
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	case FS_176400HZ:	return 0x02700;
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	case FS_192000HZ:	return 0x02400;
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	default:		return 0x0;
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	}
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}
403

404
static inline u32 AutoRstThLo(unsigned int fs)
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{
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	switch (fs) {
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	case FS_8000HZ:		return 0x30000;
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	case FS_11025HZ:	return 0x23000;
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	case FS_12000HZ:	return 0x20000;
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	case FS_16000HZ:	return 0x18000;
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	case FS_22050HZ:	return 0x11000;
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	case FS_24000HZ:	return 0x0FE00;
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	case FS_32000HZ:	return 0x0BE00;
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	case FS_44100HZ:	return 0x08A00;
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	case FS_48000HZ:	return 0x07F00;
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	case FS_88200HZ:	return 0x04500;
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	case FS_96000HZ:	return 0x04000;
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	case FS_176400HZ:	return 0x02300;
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	case FS_192000HZ:	return 0x02000;
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	default:		return 0x0;
421
	}
422
}
423

424
bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id);
425
bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id);
426

427
int mt8365_dai_i2s_register(struct mtk_base_afe *afe);
428
int mt8365_dai_set_priv(struct mtk_base_afe *afe,
429
			int id,
430
			int priv_size,
431
			const void *priv_data);
432

433
int mt8365_afe_fs_timing(unsigned int rate);
434

435
void mt8365_afe_set_i2s_out_enable(struct mtk_base_afe *afe, bool enable);
436
int mt8365_afe_set_i2s_out(struct mtk_base_afe *afe, unsigned int rate,	int bit_width);
437

438
int mt8365_dai_adda_register(struct mtk_base_afe *afe);
439
int mt8365_dai_enable_adda_on(struct mtk_base_afe *afe);
440
int mt8365_dai_disable_adda_on(struct mtk_base_afe *afe);
441

442
int mt8365_dai_dmic_register(struct mtk_base_afe *afe);
443

444
int mt8365_dai_pcm_register(struct mtk_base_afe *afe);
445

446
int mt8365_dai_tdm_register(struct mtk_base_afe *afe);
447

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#endif
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