CoCalc -- mt8365-reg.h

GitHub Repository: torvalds/linux
Path: blob/master/sound/soc/mediatek/mt8365/mt8365-reg.h
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/* SPDX-License-Identifier: GPL-2.0
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 *
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 * MediaTek 8365 audio driver reg definition
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 *
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 * Copyright (c) 2024 MediaTek Inc.
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 * Authors: Jia Zeng <[email protected]>
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 *          Alexandre Mergnat <[email protected]>
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 */
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#ifndef _MT8365_REG_H_
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#define _MT8365_REG_H_
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#include <linux/bitfield.h>
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#define AUDIO_TOP_CON0			(0x0000)
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#define AUDIO_TOP_CON1			(0x0004)
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#define AUDIO_TOP_CON2			(0x0008)
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#define AUDIO_TOP_CON3			(0x000c)
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#define AFE_DAC_CON0			(0x0010)
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#define AFE_DAC_CON1			(0x0014)
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#define AFE_I2S_CON			(0x0018)
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#define AFE_CONN0			(0x0020)
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#define AFE_CONN1			(0x0024)
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#define AFE_CONN2			(0x0028)
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#define AFE_CONN3			(0x002c)
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#define AFE_CONN4			(0x0030)
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#define AFE_I2S_CON1			(0x0034)
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#define AFE_I2S_CON2			(0x0038)
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#define AFE_MRGIF_CON			(0x003c)
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#define AFE_DL1_BASE			(0x0040)
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#define AFE_DL1_CUR			(0x0044)
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#define AFE_DL1_END			(0x0048)
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#define AFE_I2S_CON3			(0x004c)
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#define AFE_DL2_BASE			(0x0050)
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#define AFE_DL2_CUR			(0x0054)
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#define AFE_DL2_END			(0x0058)
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#define AFE_CONN5			(0x005c)
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#define AFE_AWB_BASE			(0x0070)
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#define AFE_AWB_END			(0x0078)
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#define AFE_AWB_CUR			(0x007c)
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#define AFE_VUL_BASE			(0x0080)
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#define AFE_VUL_END			(0x0088)
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#define AFE_VUL_CUR			(0x008c)
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#define AFE_CONN6			(0x00bc)
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#define AFE_MEMIF_MSB			(0x00cc)
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#define AFE_MEMIF_MON0			(0x00d0)
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#define AFE_MEMIF_MON1			(0x00d4)
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#define AFE_MEMIF_MON2			(0x00d8)
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#define AFE_MEMIF_MON3			(0x00dc)
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#define AFE_MEMIF_MON4			(0x00e0)
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#define AFE_MEMIF_MON5			(0x00e4)
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#define AFE_MEMIF_MON6			(0x00e8)
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#define AFE_MEMIF_MON7			(0x00ec)
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#define AFE_MEMIF_MON8			(0x00f0)
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#define AFE_MEMIF_MON9			(0x00f4)
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#define AFE_MEMIF_MON10			(0x00f8)
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#define AFE_MEMIF_MON11			(0x00fc)
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#define AFE_ADDA_DL_SRC2_CON0		(0x0108)
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#define AFE_ADDA_DL_SRC2_CON1		(0x010c)
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#define AFE_ADDA_UL_SRC_CON0		(0x0114)
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#define AFE_ADDA_UL_SRC_CON1		(0x0118)
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#define AFE_ADDA_TOP_CON0		(0x0120)
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#define AFE_ADDA_UL_DL_CON0		(0x0124)
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#define AFE_ADDA_SRC_DEBUG		(0x012c)
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#define AFE_ADDA_SRC_DEBUG_MON0		(0x0130)
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#define AFE_ADDA_SRC_DEBUG_MON1		(0x0134)
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#define AFE_ADDA_UL_SRC_MON0		(0x0148)
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#define AFE_ADDA_UL_SRC_MON1		(0x014c)
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#define AFE_SRAM_BOUND			(0x0170)
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#define AFE_SECURE_CON			(0x0174)
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#define AFE_SECURE_CONN0		(0x0178)
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#define AFE_SIDETONE_DEBUG		(0x01d0)
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#define AFE_SIDETONE_MON		(0x01d4)
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#define AFE_SIDETONE_CON0		(0x01e0)
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#define AFE_SIDETONE_COEFF		(0x01e4)
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#define AFE_SIDETONE_CON1		(0x01e8)
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#define AFE_SIDETONE_GAIN		(0x01ec)
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#define AFE_SGEN_CON0			(0x01f0)
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#define AFE_SINEGEN_CON_TDM		(0x01f8)
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#define AFE_SINEGEN_CON_TDM_IN		(0x01fc)
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#define AFE_TOP_CON0			(0x0200)
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#define AFE_BUS_CFG			(0x0240)
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#define AFE_BUS_MON0			(0x0244)
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#define AFE_ADDA_PREDIS_CON0		(0x0260)
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#define AFE_ADDA_PREDIS_CON1		(0x0264)
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#define AFE_CONN_MON0			(0x0280)
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#define AFE_CONN_MON1			(0x0284)
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#define AFE_CONN_MON2			(0x0288)
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#define AFE_CONN_MON3			(0x028c)
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#define AFE_ADDA_IIR_COEF_02_01		(0x0290)
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#define AFE_ADDA_IIR_COEF_04_03		(0x0294)
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#define AFE_ADDA_IIR_COEF_06_05		(0x0298)
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#define AFE_ADDA_IIR_COEF_08_07		(0x029c)
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#define AFE_ADDA_IIR_COEF_10_09		(0x02a0)
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#define AFE_VUL_D2_BASE			(0x0350)
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#define AFE_VUL_D2_END			(0x0358)
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#define AFE_VUL_D2_CUR			(0x035c)
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#define AFE_HDMI_OUT_CON0		(0x0370)
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#define AFE_HDMI_OUT_BASE		(0x0374)
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#define AFE_HDMI_OUT_CUR		(0x0378)
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#define AFE_HDMI_OUT_END		(0x037c)
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#define AFE_SPDIF_OUT_CON0		(0x0380)
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#define AFE_SPDIF_OUT_BASE		(0x0384)
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#define AFE_SPDIF_OUT_CUR		(0x0388)
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#define AFE_SPDIF_OUT_END		(0x038c)
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#define AFE_HDMI_CONN0			(0x0390)
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#define AFE_HDMI_CONN1			(0x0398)
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#define AFE_CONN_TDMIN_CON		(0x039c)
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#define AFE_IRQ_MCU_CON			(0x03a0)
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#define AFE_IRQ_MCU_STATUS		(0x03a4)
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#define AFE_IRQ_MCU_CLR			(0x03a8)
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#define AFE_IRQ_MCU_CNT1		(0x03ac)
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#define AFE_IRQ_MCU_CNT2		(0x03b0)
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#define AFE_IRQ_MCU_EN			(0x03b4)
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#define AFE_IRQ_MCU_MON2		(0x03b8)
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#define AFE_IRQ_MCU_CNT5		(0x03bc)
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#define AFE_IRQ1_MCU_CNT_MON		(0x03c0)
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#define AFE_IRQ2_MCU_CNT_MON		(0x03c4)
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#define AFE_IRQ1_MCU_EN_CNT_MON		(0x03c8)
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#define AFE_IRQ5_MCU_CNT_MON		(0x03cc)
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#define AFE_MEMIF_MINLEN		(0x03d0)
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#define AFE_MEMIF_MAXLEN		(0x03d4)
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#define AFE_MEMIF_PBUF_SIZE		(0x03d8)
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#define AFE_IRQ_MCU_CNT7		(0x03dc)
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#define AFE_IRQ7_MCU_CNT_MON		(0x03e0)
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#define AFE_MEMIF_PBUF2_SIZE		(0x03ec)
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#define AFE_APLL_TUNER_CFG		(0x03f0)
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#define AFE_APLL_TUNER_CFG1		(0x03f4)
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#define AFE_IRQ_MCU_CON2		(0x03f8)
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#define IRQ13_MCU_CNT			(0x0408)
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#define IRQ13_MCU_CNT_MON		(0x040c)
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#define AFE_GAIN1_CON0			(0x0410)
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#define AFE_GAIN1_CON1			(0x0414)
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#define AFE_GAIN1_CON2			(0x0418)
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#define AFE_GAIN1_CON3			(0x041c)
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#define AFE_GAIN2_CON0			(0x0428)
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#define AFE_GAIN2_CON1			(0x042c)
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#define AFE_GAIN2_CON2			(0x0430)
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#define AFE_GAIN2_CON3			(0x0434)
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#define AFE_GAIN2_CUR			(0x043c)
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#define AFE_CONN11			(0x0448)
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#define AFE_CONN12			(0x044c)
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#define AFE_CONN13			(0x0450)
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#define AFE_CONN14			(0x0454)
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#define AFE_CONN15			(0x0458)
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#define AFE_CONN16			(0x045c)
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#define AFE_CONN7			(0x0460)
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#define AFE_CONN8			(0x0464)
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#define AFE_CONN9			(0x0468)
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#define AFE_CONN10			(0x046c)
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#define AFE_CONN21			(0x0470)
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#define AFE_CONN22			(0x0474)
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#define AFE_CONN23			(0x0478)
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#define AFE_CONN24			(0x047c)
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#define AFE_IEC_CFG			(0x0480)
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#define AFE_IEC_NSNUM			(0x0484)
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#define AFE_IEC_BURST_INFO		(0x0488)
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#define AFE_IEC_BURST_LEN		(0x048c)
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#define AFE_IEC_NSADR			(0x0490)
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#define AFE_CONN_RS			(0x0494)
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#define AFE_CONN_DI			(0x0498)
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#define AFE_IEC_CHL_STAT0		(0x04a0)
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#define AFE_IEC_CHL_STAT1		(0x04a4)
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#define AFE_IEC_CHR_STAT0		(0x04a8)
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#define AFE_IEC_CHR_STAT1		(0x04ac)
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#define AFE_CONN25			(0x04b0)
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#define AFE_CONN26			(0x04b4)
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#define FPGA_CFG2			(0x04b8)
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#define FPGA_CFG3			(0x04bc)
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#define FPGA_CFG0			(0x04c0)
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#define FPGA_CFG1			(0x04c4)
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#define AFE_SRAM_DELSEL_CON0		(0x04f0)
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#define AFE_SRAM_DELSEL_CON1		(0x04f4)
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#define AFE_SRAM_DELSEL_CON2		(0x04f8)
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#define FPGA_CFG4			(0x04fc)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON0	(0x0500)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON1	(0x0504)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON2	(0x0508)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON3	(0x050c)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON4	(0x0510)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON5	(0x0514)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON6	(0x0518)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON7	(0x051c)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON8	(0x0520)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON9	(0x0524)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON10	(0x0528)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON12	(0x0530)
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#define AFE_TDM_GASRC4_ASRC_2CH_CON13	(0x0534)
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#define PCM_INTF_CON2			(0x0538)
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#define PCM2_INTF_CON			(0x053c)
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#define AFE_APB_MON			(0x0540)
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#define AFE_CONN34			(0x0544)
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#define AFE_TDM_CON1			(0x0548)
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#define AFE_TDM_CON2			(0x054c)
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#define PCM_INTF_CON1			(0x0550)
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#define AFE_SECURE_MASK_CONN47_1	(0x0554)
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#define AFE_SECURE_MASK_CONN48_1	(0x0558)
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#define AFE_SECURE_MASK_CONN49_1	(0x055c)
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#define AFE_SECURE_MASK_CONN50_1	(0x0560)
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#define AFE_SECURE_MASK_CONN51_1	(0x0564)
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#define AFE_SECURE_MASK_CONN52_1	(0x0568)
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#define AFE_SECURE_MASK_CONN53_1	(0x056c)
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#define AFE_SE_SECURE_CON		(0x0570)
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#define AFE_TDM_IN_CON1			(0x0588)
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#define AFE_TDM_IN_CON2			(0x058c)
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#define AFE_TDM_IN_MON1			(0x0590)
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#define AFE_TDM_IN_MON2			(0x0594)
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#define AFE_TDM_IN_MON3			(0x0598)
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#define AFE_DMIC0_UL_SRC_CON0		(0x05b4)
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#define AFE_DMIC0_UL_SRC_CON1		(0x05b8)
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#define AFE_DMIC0_SRC_DEBUG		(0x05bc)
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#define AFE_DMIC0_SRC_DEBUG_MON0	(0x05c0)
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#define AFE_DMIC0_UL_SRC_MON0		(0x05c8)
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#define AFE_DMIC0_UL_SRC_MON1		(0x05cc)
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#define AFE_DMIC0_IIR_COEF_02_01	(0x05d0)
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#define AFE_DMIC0_IIR_COEF_04_03	(0x05d4)
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#define AFE_DMIC0_IIR_COEF_06_05	(0x05d8)
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#define AFE_DMIC0_IIR_COEF_08_07	(0x05dc)
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#define AFE_DMIC0_IIR_COEF_10_09	(0x05e0)
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#define AFE_DMIC1_UL_SRC_CON0		(0x0620)
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#define AFE_DMIC1_UL_SRC_CON1		(0x0624)
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#define AFE_DMIC1_SRC_DEBUG		(0x0628)
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#define AFE_DMIC1_SRC_DEBUG_MON0	(0x062c)
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#define AFE_DMIC1_UL_SRC_MON0		(0x0634)
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#define AFE_DMIC1_UL_SRC_MON1		(0x0638)
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#define AFE_DMIC1_IIR_COEF_02_01	(0x063c)
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#define AFE_DMIC1_IIR_COEF_04_03	(0x0640)
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#define AFE_DMIC1_IIR_COEF_06_05	(0x0644)
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#define AFE_DMIC1_IIR_COEF_08_07	(0x0648)
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#define AFE_DMIC1_IIR_COEF_10_09	(0x064c)
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#define AFE_SECURE_MASK_CONN39_1	(0x068c)
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#define AFE_SECURE_MASK_CONN40_1	(0x0690)
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#define AFE_SECURE_MASK_CONN41_1	(0x0694)
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#define AFE_SECURE_MASK_CONN42_1	(0x0698)
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#define AFE_SECURE_MASK_CONN43_1	(0x069c)
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#define AFE_SECURE_MASK_CONN44_1	(0x06a0)
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#define AFE_SECURE_MASK_CONN45_1	(0x06a4)
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#define AFE_SECURE_MASK_CONN46_1	(0x06a8)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON0	(0x06c0)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON1	(0x06c4)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON2	(0x06c8)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON3	(0x06cc)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON4	(0x06d0)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON5	(0x06d4)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON6	(0x06d8)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON7	(0x06dc)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON8	(0x06e0)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON9	(0x06e4)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON10	(0x06e8)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON12	(0x06f0)
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#define AFE_TDM_GASRC1_ASRC_2CH_CON13	(0x06f4)
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#define AFE_TDM_ASRC_CON0		(0x06f8)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON0	(0x0700)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON1	(0x0704)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON2	(0x0708)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON3	(0x070c)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON4	(0x0710)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON5	(0x0714)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON6	(0x0718)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON7	(0x071c)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON8	(0x0720)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON9	(0x0724)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON10	(0x0728)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON12	(0x0730)
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#define AFE_TDM_GASRC2_ASRC_2CH_CON13	(0x0734)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON0	(0x0740)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON1	(0x0744)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON2	(0x0748)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON3	(0x074c)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON4	(0x0750)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON5	(0x0754)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON6	(0x0758)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON7	(0x075c)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON8	(0x0760)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON9	(0x0764)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON10	(0x0768)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON12	(0x0770)
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#define AFE_TDM_GASRC3_ASRC_2CH_CON13	(0x0774)
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#define AFE_DMIC2_UL_SRC_CON0		(0x0780)
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#define AFE_DMIC2_UL_SRC_CON1		(0x0784)
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#define AFE_DMIC2_SRC_DEBUG		(0x0788)
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#define AFE_DMIC2_SRC_DEBUG_MON0	(0x078c)
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#define AFE_DMIC2_UL_SRC_MON0		(0x0794)
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#define AFE_DMIC2_UL_SRC_MON1		(0x0798)
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#define AFE_DMIC2_IIR_COEF_02_01	(0x079c)
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#define AFE_DMIC2_IIR_COEF_04_03	(0x07a0)
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#define AFE_DMIC2_IIR_COEF_06_05	(0x07a4)
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#define AFE_DMIC2_IIR_COEF_08_07	(0x07a8)
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#define AFE_DMIC2_IIR_COEF_10_09	(0x07ac)
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#define AFE_DMIC3_UL_SRC_CON0		(0x07ec)
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#define AFE_DMIC3_UL_SRC_CON1		(0x07f0)
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#define AFE_DMIC3_SRC_DEBUG		(0x07f4)
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#define AFE_DMIC3_SRC_DEBUG_MON0	(0x07f8)
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#define AFE_DMIC3_UL_SRC_MON0		(0x0800)
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#define AFE_DMIC3_UL_SRC_MON1		(0x0804)
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#define AFE_DMIC3_IIR_COEF_02_01	(0x0808)
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#define AFE_DMIC3_IIR_COEF_04_03	(0x080c)
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#define AFE_DMIC3_IIR_COEF_06_05	(0x0810)
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#define AFE_DMIC3_IIR_COEF_08_07	(0x0814)
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#define AFE_DMIC3_IIR_COEF_10_09	(0x0818)
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#define AFE_SECURE_MASK_CONN25_1	(0x0858)
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#define AFE_SECURE_MASK_CONN26_1	(0x085c)
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#define AFE_SECURE_MASK_CONN27_1	(0x0860)
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#define AFE_SECURE_MASK_CONN28_1	(0x0864)
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#define AFE_SECURE_MASK_CONN29_1	(0x0868)
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#define AFE_SECURE_MASK_CONN30_1	(0x086c)
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#define AFE_SECURE_MASK_CONN31_1	(0x0870)
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#define AFE_SECURE_MASK_CONN32_1	(0x0874)
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#define AFE_SECURE_MASK_CONN33_1	(0x0878)
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#define AFE_SECURE_MASK_CONN34_1	(0x087c)
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#define AFE_SECURE_MASK_CONN35_1	(0x0880)
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#define AFE_SECURE_MASK_CONN36_1	(0x0884)
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#define AFE_SECURE_MASK_CONN37_1	(0x0888)
315
#define AFE_SECURE_MASK_CONN38_1	(0x088c)
316
#define AFE_IRQ_MCU_SCP_EN		(0x0890)
317
#define AFE_IRQ_MCU_DSP_EN		(0x0894)
318
#define AFE_IRQ3_MCU_CNT_MON		(0x0898)
319
#define AFE_IRQ4_MCU_CNT_MON		(0x089c)
320
#define AFE_IRQ8_MCU_CNT_MON		(0x08a0)
321
#define AFE_IRQ_MCU_CNT3		(0x08a4)
322
#define AFE_IRQ_MCU_CNT4		(0x08a8)
323
#define AFE_IRQ_MCU_CNT8		(0x08ac)
324
#define AFE_IRQ_MCU_CNT11		(0x08b0)
325
#define AFE_IRQ_MCU_CNT12		(0x08b4)
326
#define AFE_IRQ11_MCU_CNT_MON		(0x08b8)
327
#define AFE_IRQ12_MCU_CNT_MON		(0x08bc)
328
#define AFE_VUL3_BASE			(0x08c0)
329
#define AFE_VUL3_CUR			(0x08c4)
330
#define AFE_VUL3_END			(0x08c8)
331
#define AFE_VUL3_BASE_MSB		(0x08d0)
332
#define AFE_VUL3_END_MSB		(0x08d4)
333
#define AFE_IRQ10_MCU_CNT_MON		(0x08d8)
334
#define AFE_IRQ_MCU_CNT10		(0x08dc)
335
#define AFE_IRQ_ACC1_CNT		(0x08e0)
336
#define AFE_IRQ_ACC2_CNT		(0x08e4)
337
#define AFE_IRQ_ACC1_CNT_MON1		(0x08e8)
338
#define AFE_IRQ_ACC2_CNT_MON		(0x08ec)
339
#define AFE_TSF_CON			(0x08f0)
340
#define AFE_TSF_MON			(0x08f4)
341
#define AFE_IRQ_ACC1_CNT_MON2		(0x08f8)
342
#define AFE_SPDIFIN_CFG0		(0x0900)
343
#define AFE_SPDIFIN_CFG1		(0x0904)
344
#define AFE_SPDIFIN_CHSTS1		(0x0908)
345
#define AFE_SPDIFIN_CHSTS2		(0x090c)
346
#define AFE_SPDIFIN_CHSTS3		(0x0910)
347
#define AFE_SPDIFIN_CHSTS4		(0x0914)
348
#define AFE_SPDIFIN_CHSTS5		(0x0918)
349
#define AFE_SPDIFIN_CHSTS6		(0x091c)
350
#define AFE_SPDIFIN_DEBUG1		(0x0920)
351
#define AFE_SPDIFIN_DEBUG2		(0x0924)
352
#define AFE_SPDIFIN_DEBUG3		(0x0928)
353
#define AFE_SPDIFIN_DEBUG4		(0x092c)
354
#define AFE_SPDIFIN_EC			(0x0930)
355
#define AFE_SPDIFIN_CKLOCK_CFG		(0x0934)
356
#define AFE_SPDIFIN_BR			(0x093c)
357
#define AFE_SPDIFIN_BR_DBG1		(0x0940)
358
#define AFE_SPDIFIN_INT_EXT		(0x0948)
359
#define AFE_SPDIFIN_INT_EXT2		(0x094c)
360
#define SPDIFIN_FREQ_INFO		(0x0950)
361
#define SPDIFIN_FREQ_INFO_2		(0x0954)
362
#define SPDIFIN_FREQ_INFO_3		(0x0958)
363
#define SPDIFIN_FREQ_STATUS		(0x095c)
364
#define SPDIFIN_USERCODE1		(0x0960)
365
#define SPDIFIN_USERCODE2		(0x0964)
366
#define SPDIFIN_USERCODE3		(0x0968)
367
#define SPDIFIN_USERCODE4		(0x096c)
368
#define SPDIFIN_USERCODE5		(0x0970)
369
#define SPDIFIN_USERCODE6		(0x0974)
370
#define SPDIFIN_USERCODE7		(0x0978)
371
#define SPDIFIN_USERCODE8		(0x097c)
372
#define SPDIFIN_USERCODE9		(0x0980)
373
#define SPDIFIN_USERCODE10		(0x0984)
374
#define SPDIFIN_USERCODE11		(0x0988)
375
#define SPDIFIN_USERCODE12		(0x098c)
376
#define SPDIFIN_MEMIF_CON0		(0x0990)
377
#define SPDIFIN_BASE_ADR		(0x0994)
378
#define SPDIFIN_END_ADR			(0x0998)
379
#define SPDIFIN_APLL_TUNER_CFG		(0x09a0)
380
#define SPDIFIN_APLL_TUNER_CFG1		(0x09a4)
381
#define SPDIFIN_APLL2_TUNER_CFG		(0x09a8)
382
#define SPDIFIN_APLL2_TUNER_CFG1	(0x09ac)
383
#define SPDIFIN_TYPE_DET		(0x09b0)
384
#define MPHONE_MULTI_CON0		(0x09b4)
385
#define SPDIFIN_CUR_ADR			(0x09b8)
386
#define AFE_SINEGEN_CON_SPDIFIN		(0x09bc)
387
#define AFE_HDMI_IN_2CH_CON0		(0x09c0)
388
#define AFE_HDMI_IN_2CH_BASE		(0x09c4)
389
#define AFE_HDMI_IN_2CH_END		(0x09c8)
390
#define AFE_HDMI_IN_2CH_CUR		(0x09cc)
391
#define AFE_MEMIF_BUF_MON0		(0x09d0)
392
#define AFE_MEMIF_BUF_MON1		(0x09d4)
393
#define AFE_MEMIF_BUF_MON2		(0x09d8)
394
#define AFE_MEMIF_BUF_MON3		(0x09dc)
395
#define AFE_MEMIF_BUF_MON6		(0x09e8)
396
#define AFE_MEMIF_BUF_MON7		(0x09ec)
397
#define AFE_MEMIF_BUF_MON8		(0x09f0)
398
#define AFE_MEMIF_BUF_MON10		(0x09f8)
399
#define AFE_MEMIF_BUF_MON11		(0x09fc)
400
#define SYSTOP_STC_CONFIG		(0x0a00)
401
#define AUDIO_STC_STATUS		(0x0a04)
402
#define SYSTOP_W_STC_H			(0x0a08)
403
#define SYSTOP_W_STC_L			(0x0a0c)
404
#define SYSTOP_R_STC_H			(0x0a10)
405
#define SYSTOP_R_STC_L			(0x0a14)
406
#define AUDIO_W_STC_H			(0x0a18)
407
#define AUDIO_W_STC_L			(0x0a1c)
408
#define AUDIO_R_STC_H			(0x0a20)
409
#define AUDIO_R_STC_L			(0x0a24)
410
#define SYSTOP_W_STC2_H			(0x0a28)
411
#define SYSTOP_W_STC2_L			(0x0a2c)
412
#define SYSTOP_R_STC2_H			(0x0a30)
413
#define SYSTOP_R_STC2_L			(0x0a34)
414
#define AUDIO_W_STC2_H			(0x0a38)
415
#define AUDIO_W_STC2_L			(0x0a3c)
416
#define AUDIO_R_STC2_H			(0x0a40)
417
#define AUDIO_R_STC2_L			(0x0a44)
418

419
#define AFE_CONN17			(0x0a48)
420
#define AFE_CONN18			(0x0a4c)
421
#define AFE_CONN19			(0x0a50)
422
#define AFE_CONN20			(0x0a54)
423
#define AFE_CONN27			(0x0a58)
424
#define AFE_CONN28			(0x0a5c)
425
#define AFE_CONN29			(0x0a60)
426
#define AFE_CONN30			(0x0a64)
427
#define AFE_CONN31			(0x0a68)
428
#define AFE_CONN32			(0x0a6c)
429
#define AFE_CONN33			(0x0a70)
430
#define AFE_CONN35			(0x0a74)
431
#define AFE_CONN36			(0x0a78)
432
#define AFE_CONN37			(0x0a7c)
433
#define AFE_CONN38			(0x0a80)
434
#define AFE_CONN39			(0x0a84)
435
#define AFE_CONN40			(0x0a88)
436
#define AFE_CONN41			(0x0a8c)
437
#define AFE_CONN42			(0x0a90)
438
#define AFE_CONN44			(0x0a94)
439
#define AFE_CONN45			(0x0a98)
440
#define AFE_CONN46			(0x0a9c)
441
#define AFE_CONN47			(0x0aa0)
442
#define AFE_CONN_24BIT			(0x0aa4)
443
#define AFE_CONN0_1			(0x0aa8)
444
#define AFE_CONN1_1			(0x0aac)
445
#define AFE_CONN2_1			(0x0ab0)
446
#define AFE_CONN3_1			(0x0ab4)
447
#define AFE_CONN4_1			(0x0ab8)
448
#define AFE_CONN5_1			(0x0abc)
449
#define AFE_CONN6_1			(0x0ac0)
450
#define AFE_CONN7_1			(0x0ac4)
451
#define AFE_CONN8_1			(0x0ac8)
452
#define AFE_CONN9_1			(0x0acc)
453
#define AFE_CONN10_1			(0x0ad0)
454
#define AFE_CONN11_1			(0x0ad4)
455
#define AFE_CONN12_1			(0x0ad8)
456
#define AFE_CONN13_1			(0x0adc)
457
#define AFE_CONN14_1			(0x0ae0)
458
#define AFE_CONN15_1			(0x0ae4)
459
#define AFE_CONN16_1			(0x0ae8)
460
#define AFE_CONN17_1			(0x0aec)
461
#define AFE_CONN18_1			(0x0af0)
462
#define AFE_CONN19_1			(0x0af4)
463
#define AFE_CONN43			(0x0af8)
464
#define AFE_CONN43_1			(0x0afc)
465
#define AFE_CONN21_1			(0x0b00)
466
#define AFE_CONN22_1			(0x0b04)
467
#define AFE_CONN23_1			(0x0b08)
468
#define AFE_CONN24_1			(0x0b0c)
469
#define AFE_CONN25_1			(0x0b10)
470
#define AFE_CONN26_1			(0x0b14)
471
#define AFE_CONN27_1			(0x0b18)
472
#define AFE_CONN28_1			(0x0b1c)
473
#define AFE_CONN29_1			(0x0b20)
474
#define AFE_CONN30_1			(0x0b24)
475
#define AFE_CONN31_1			(0x0b28)
476
#define AFE_CONN32_1			(0x0b2c)
477
#define AFE_CONN33_1			(0x0b30)
478
#define AFE_CONN34_1			(0x0b34)
479
#define AFE_CONN35_1			(0x0b38)
480
#define AFE_CONN36_1			(0x0b3c)
481
#define AFE_CONN37_1			(0x0b40)
482
#define AFE_CONN38_1			(0x0b44)
483
#define AFE_CONN39_1			(0x0b48)
484
#define AFE_CONN40_1			(0x0b4c)
485
#define AFE_CONN41_1			(0x0b50)
486
#define AFE_CONN42_1			(0x0b54)
487
#define AFE_CONN44_1			(0x0b58)
488
#define AFE_CONN45_1			(0x0b5c)
489
#define AFE_CONN46_1			(0x0b60)
490
#define AFE_CONN47_1			(0x0b64)
491
#define AFE_CONN_RS_1			(0x0b68)
492
#define AFE_CONN_DI_1			(0x0b6c)
493
#define AFE_CONN_24BIT_1		(0x0b70)
494
#define AFE_GAIN1_CUR			(0x0b78)
495
#define AFE_CONN20_1			(0x0b7c)
496
#define AFE_DL1_BASE_MSB		(0x0b80)
497
#define AFE_DL1_END_MSB			(0x0b84)
498
#define AFE_DL2_BASE_MSB		(0x0b88)
499
#define AFE_DL2_END_MSB			(0x0b8c)
500
#define AFE_AWB_BASE_MSB		(0x0b90)
501
#define AFE_AWB_END_MSB			(0x0b94)
502
#define AFE_VUL_BASE_MSB		(0x0ba0)
503
#define AFE_VUL_END_MSB			(0x0ba4)
504
#define AFE_VUL_D2_BASE_MSB		(0x0ba8)
505
#define AFE_VUL_D2_END_MSB		(0x0bac)
506
#define AFE_HDMI_OUT_BASE_MSB		(0x0bb8)
507
#define AFE_HDMI_OUT_END_MSB		(0x0bbc)
508
#define AFE_HDMI_IN_2CH_BASE_MSB	(0x0bc0)
509
#define AFE_HDMI_IN_2CH_END_MSB		(0x0bc4)
510
#define AFE_SPDIF_OUT_BASE_MSB		(0x0bc8)
511
#define AFE_SPDIF_OUT_END_MSB		(0x0bcc)
512
#define SPDIFIN_BASE_MSB		(0x0bd0)
513
#define SPDIFIN_END_MSB			(0x0bd4)
514
#define AFE_DL1_CUR_MSB			(0x0bd8)
515
#define AFE_DL2_CUR_MSB			(0x0bdc)
516
#define AFE_AWB_CUR_MSB			(0x0be8)
517
#define AFE_VUL_CUR_MSB			(0x0bf8)
518
#define AFE_VUL_D2_CUR_MSB		(0x0c04)
519
#define AFE_HDMI_OUT_CUR_MSB		(0x0c0c)
520
#define AFE_HDMI_IN_2CH_CUR_MSB		(0x0c10)
521
#define AFE_SPDIF_OUT_CUR_MSB		(0x0c14)
522
#define SPDIFIN_CUR_MSB			(0x0c18)
523
#define AFE_CONN_REG			(0x0c20)
524
#define AFE_SECURE_MASK_CONN14_1	(0x0c24)
525
#define AFE_SECURE_MASK_CONN15_1	(0x0c28)
526
#define AFE_SECURE_MASK_CONN16_1	(0x0c2c)
527
#define AFE_SECURE_MASK_CONN17_1	(0x0c30)
528
#define AFE_SECURE_MASK_CONN18_1	(0x0c34)
529
#define AFE_SECURE_MASK_CONN19_1	(0x0c38)
530
#define AFE_SECURE_MASK_CONN20_1	(0x0c3c)
531
#define AFE_SECURE_MASK_CONN21_1	(0x0c40)
532
#define AFE_SECURE_MASK_CONN22_1	(0x0c44)
533
#define AFE_SECURE_MASK_CONN23_1	(0x0c48)
534
#define AFE_SECURE_MASK_CONN24_1	(0x0c4c)
535
#define AFE_ADDA_DL_SDM_DCCOMP_CON	(0x0c50)
536
#define AFE_ADDA_DL_SDM_TEST		(0x0c54)
537
#define AFE_ADDA_DL_DC_COMP_CFG0	(0x0c58)
538
#define AFE_ADDA_DL_DC_COMP_CFG1	(0x0c5c)
539
#define AFE_ADDA_DL_SDM_FIFO_MON	(0x0c60)
540
#define AFE_ADDA_DL_SRC_LCH_MON		(0x0c64)
541
#define AFE_ADDA_DL_SRC_RCH_MON		(0x0c68)
542
#define AFE_ADDA_DL_SDM_OUT_MON		(0x0c6c)
543
#define AFE_ADDA_DL_SDM_DITHER_CON	(0x0c70)
544

545
#define AFE_VUL3_CUR_MSB		(0x0c78)
546
#define AFE_ASRC_2CH_CON0		(0x0c80)
547
#define AFE_ASRC_2CH_CON1		(0x0c84)
548
#define AFE_ASRC_2CH_CON2		(0x0c88)
549
#define AFE_ASRC_2CH_CON3		(0x0c8c)
550
#define AFE_ASRC_2CH_CON4		(0x0c90)
551
#define AFE_ASRC_2CH_CON5		(0x0c94)
552
#define AFE_ASRC_2CH_CON6		(0x0c98)
553
#define AFE_ASRC_2CH_CON7		(0x0c9c)
554
#define AFE_ASRC_2CH_CON8		(0x0ca0)
555
#define AFE_ASRC_2CH_CON9		(0x0ca4)
556
#define AFE_ASRC_2CH_CON10		(0x0ca8)
557
#define AFE_ASRC_2CH_CON12		(0x0cb0)
558
#define AFE_ASRC_2CH_CON13		(0x0cb4)
559

560
#define AFE_PCM_TX_ASRC_2CH_CON0	(0x0cc0)
561
#define AFE_PCM_TX_ASRC_2CH_CON1	(0x0cc4)
562
#define AFE_PCM_TX_ASRC_2CH_CON2	(0x0cc8)
563
#define AFE_PCM_TX_ASRC_2CH_CON3	(0x0ccc)
564
#define AFE_PCM_TX_ASRC_2CH_CON4	(0x0cd0)
565
#define AFE_PCM_TX_ASRC_2CH_CON5	(0x0cd4)
566
#define AFE_PCM_TX_ASRC_2CH_CON6	(0x0cd8)
567
#define AFE_PCM_TX_ASRC_2CH_CON7	(0x0cdc)
568
#define AFE_PCM_TX_ASRC_2CH_CON8	(0x0ce0)
569
#define AFE_PCM_TX_ASRC_2CH_CON9	(0x0ce4)
570
#define AFE_PCM_TX_ASRC_2CH_CON10	(0x0ce8)
571
#define AFE_PCM_TX_ASRC_2CH_CON12	(0x0cf0)
572
#define AFE_PCM_TX_ASRC_2CH_CON13	(0x0cf4)
573
#define AFE_PCM_RX_ASRC_2CH_CON0	(0x0d00)
574
#define AFE_PCM_RX_ASRC_2CH_CON1	(0x0d04)
575
#define AFE_PCM_RX_ASRC_2CH_CON2	(0x0d08)
576
#define AFE_PCM_RX_ASRC_2CH_CON3	(0x0d0c)
577
#define AFE_PCM_RX_ASRC_2CH_CON4	(0x0d10)
578
#define AFE_PCM_RX_ASRC_2CH_CON5	(0x0d14)
579
#define AFE_PCM_RX_ASRC_2CH_CON6	(0x0d18)
580
#define AFE_PCM_RX_ASRC_2CH_CON7	(0x0d1c)
581
#define AFE_PCM_RX_ASRC_2CH_CON8	(0x0d20)
582
#define AFE_PCM_RX_ASRC_2CH_CON9	(0x0d24)
583
#define AFE_PCM_RX_ASRC_2CH_CON10	(0x0d28)
584
#define AFE_PCM_RX_ASRC_2CH_CON12	(0x0d30)
585
#define AFE_PCM_RX_ASRC_2CH_CON13	(0x0d34)
586

587
#define AFE_ADDA_PREDIS_CON2		(0x0d40)
588
#define AFE_ADDA_PREDIS_CON3		(0x0d44)
589
#define AFE_SECURE_MASK_CONN4_1		(0x0d48)
590
#define AFE_SECURE_MASK_CONN5_1		(0x0d4c)
591
#define AFE_SECURE_MASK_CONN6_1		(0x0d50)
592
#define AFE_SECURE_MASK_CONN7_1		(0x0d54)
593
#define AFE_SECURE_MASK_CONN8_1		(0x0d58)
594
#define AFE_SECURE_MASK_CONN9_1		(0x0d5c)
595
#define AFE_SECURE_MASK_CONN10_1	(0x0d60)
596
#define AFE_SECURE_MASK_CONN11_1	(0x0d64)
597
#define AFE_SECURE_MASK_CONN12_1	(0x0d68)
598
#define AFE_SECURE_MASK_CONN13_1	(0x0d6c)
599
#define AFE_MEMIF_MON12			(0x0d70)
600
#define AFE_MEMIF_MON13			(0x0d74)
601
#define AFE_MEMIF_MON14			(0x0d78)
602
#define AFE_MEMIF_MON15			(0x0d7c)
603
#define AFE_SECURE_MASK_CONN42		(0x0dbc)
604
#define AFE_SECURE_MASK_CONN43		(0x0dc0)
605
#define AFE_SECURE_MASK_CONN44		(0x0dc4)
606
#define AFE_SECURE_MASK_CONN45		(0x0dc8)
607
#define AFE_SECURE_MASK_CONN46		(0x0dcc)
608
#define AFE_HD_ENGEN_ENABLE		(0x0dd0)
609
#define AFE_SECURE_MASK_CONN47		(0x0dd4)
610
#define AFE_SECURE_MASK_CONN48		(0x0dd8)
611
#define AFE_SECURE_MASK_CONN49		(0x0ddc)
612
#define AFE_SECURE_MASK_CONN50		(0x0de0)
613
#define AFE_SECURE_MASK_CONN51		(0x0de4)
614
#define AFE_SECURE_MASK_CONN52		(0x0de8)
615
#define AFE_SECURE_MASK_CONN53		(0x0dec)
616
#define AFE_SECURE_MASK_CONN0_1		(0x0df0)
617
#define AFE_SECURE_MASK_CONN1_1		(0x0df4)
618
#define AFE_SECURE_MASK_CONN2_1		(0x0df8)
619
#define AFE_SECURE_MASK_CONN3_1		(0x0dfc)
620

621
#define AFE_ADDA_MTKAIF_CFG0		(0x0e00)
622
#define AFE_ADDA_MTKAIF_SYNCWORD_CFG	(0x0e14)
623
#define AFE_ADDA_MTKAIF_RX_CFG0		(0x0e20)
624
#define AFE_ADDA_MTKAIF_RX_CFG1		(0x0e24)
625
#define AFE_ADDA_MTKAIF_RX_CFG2		(0x0e28)
626
#define AFE_ADDA_MTKAIF_MON0		(0x0e34)
627
#define AFE_ADDA_MTKAIF_MON1		(0x0e38)
628
#define AFE_AUD_PAD_TOP			(0x0e40)
629

630
#define AFE_CM1_CON4			(0x0e48)
631
#define AFE_CM2_CON4			(0x0e4c)
632
#define AFE_CM1_CON0			(0x0e50)
633
#define AFE_CM1_CON1			(0x0e54)
634
#define AFE_CM1_CON2			(0x0e58)
635
#define AFE_CM1_CON3			(0x0e5c)
636
#define AFE_CM2_CON0			(0x0e60)
637
#define AFE_CM2_CON1			(0x0e64)
638
#define AFE_CM2_CON2			(0x0e68)
639
#define AFE_CM2_CON3			(0x0e6c)
640
#define AFE_CM2_CONN0			(0x0e70)
641
#define AFE_CM2_CONN1			(0x0e74)
642
#define AFE_CM2_CONN2			(0x0e78)
643

644
#define AFE_GENERAL1_ASRC_2CH_CON0	(0x0e80)
645
#define AFE_GENERAL1_ASRC_2CH_CON1	(0x0e84)
646
#define AFE_GENERAL1_ASRC_2CH_CON2	(0x0e88)
647
#define AFE_GENERAL1_ASRC_2CH_CON3	(0x0e8c)
648
#define AFE_GENERAL1_ASRC_2CH_CON4	(0x0e90)
649
#define AFE_GENERAL1_ASRC_2CH_CON5	(0x0e94)
650
#define AFE_GENERAL1_ASRC_2CH_CON6	(0x0e98)
651
#define AFE_GENERAL1_ASRC_2CH_CON7	(0x0e9c)
652
#define AFE_GENERAL1_ASRC_2CH_CON8	(0x0ea0)
653
#define AFE_GENERAL1_ASRC_2CH_CON9	(0x0ea4)
654
#define AFE_GENERAL1_ASRC_2CH_CON10	(0x0ea8)
655
#define AFE_GENERAL1_ASRC_2CH_CON12	(0x0eb0)
656
#define AFE_GENERAL1_ASRC_2CH_CON13	(0x0eb4)
657
#define GENERAL_ASRC_MODE		(0x0eb8)
658
#define GENERAL_ASRC_EN_ON		(0x0ebc)
659

660
#define AFE_CONN48			(0x0ec0)
661
#define AFE_CONN49			(0x0ec4)
662
#define AFE_CONN50			(0x0ec8)
663
#define AFE_CONN51			(0x0ecc)
664
#define AFE_CONN52			(0x0ed0)
665
#define AFE_CONN53			(0x0ed4)
666
#define AFE_CONN48_1			(0x0ee0)
667
#define AFE_CONN49_1			(0x0ee4)
668
#define AFE_CONN50_1			(0x0ee8)
669
#define AFE_CONN51_1			(0x0eec)
670
#define AFE_CONN52_1			(0x0ef0)
671
#define AFE_CONN53_1			(0x0ef4)
672

673
#define AFE_GENERAL2_ASRC_2CH_CON0	(0x0f00)
674
#define AFE_GENERAL2_ASRC_2CH_CON1	(0x0f04)
675
#define AFE_GENERAL2_ASRC_2CH_CON2	(0x0f08)
676
#define AFE_GENERAL2_ASRC_2CH_CON3	(0x0f0c)
677
#define AFE_GENERAL2_ASRC_2CH_CON4	(0x0f10)
678
#define AFE_GENERAL2_ASRC_2CH_CON5	(0x0f14)
679
#define AFE_GENERAL2_ASRC_2CH_CON6	(0x0f18)
680
#define AFE_GENERAL2_ASRC_2CH_CON7	(0x0f1c)
681
#define AFE_GENERAL2_ASRC_2CH_CON8	(0x0f20)
682
#define AFE_GENERAL2_ASRC_2CH_CON9	(0x0f24)
683
#define AFE_GENERAL2_ASRC_2CH_CON10	(0x0f28)
684
#define AFE_GENERAL2_ASRC_2CH_CON12	(0x0f30)
685
#define AFE_GENERAL2_ASRC_2CH_CON13	(0x0f34)
686

687
#define AFE_SECURE_MASK_CONN28		(0x0f48)
688
#define AFE_SECURE_MASK_CONN29		(0x0f4c)
689
#define AFE_SECURE_MASK_CONN30		(0x0f50)
690
#define AFE_SECURE_MASK_CONN31		(0x0f54)
691
#define AFE_SECURE_MASK_CONN32		(0x0f58)
692
#define AFE_SECURE_MASK_CONN33		(0x0f5c)
693
#define AFE_SECURE_MASK_CONN34		(0x0f60)
694
#define AFE_SECURE_MASK_CONN35		(0x0f64)
695
#define AFE_SECURE_MASK_CONN36		(0x0f68)
696
#define AFE_SECURE_MASK_CONN37		(0x0f6c)
697
#define AFE_SECURE_MASK_CONN38		(0x0f70)
698
#define AFE_SECURE_MASK_CONN39		(0x0f74)
699
#define AFE_SECURE_MASK_CONN40		(0x0f78)
700
#define AFE_SECURE_MASK_CONN41		(0x0f7c)
701
#define AFE_SIDEBAND0			(0x0f80)
702
#define AFE_SIDEBAND1			(0x0f84)
703
#define AFE_SECURE_SIDEBAND0		(0x0f88)
704
#define AFE_SECURE_SIDEBAND1		(0x0f8c)
705
#define AFE_SECURE_MASK_CONN0		(0x0f90)
706
#define AFE_SECURE_MASK_CONN1		(0x0f94)
707
#define AFE_SECURE_MASK_CONN2		(0x0f98)
708
#define AFE_SECURE_MASK_CONN3		(0x0f9c)
709
#define AFE_SECURE_MASK_CONN4		(0x0fa0)
710
#define AFE_SECURE_MASK_CONN5		(0x0fa4)
711
#define AFE_SECURE_MASK_CONN6		(0x0fa8)
712
#define AFE_SECURE_MASK_CONN7		(0x0fac)
713
#define AFE_SECURE_MASK_CONN8		(0x0fb0)
714
#define AFE_SECURE_MASK_CONN9		(0x0fb4)
715
#define AFE_SECURE_MASK_CONN10		(0x0fb8)
716
#define AFE_SECURE_MASK_CONN11		(0x0fbc)
717
#define AFE_SECURE_MASK_CONN12		(0x0fc0)
718
#define AFE_SECURE_MASK_CONN13		(0x0fc4)
719
#define AFE_SECURE_MASK_CONN14		(0x0fc8)
720
#define AFE_SECURE_MASK_CONN15		(0x0fcc)
721
#define AFE_SECURE_MASK_CONN16		(0x0fd0)
722
#define AFE_SECURE_MASK_CONN17		(0x0fd4)
723
#define AFE_SECURE_MASK_CONN18		(0x0fd8)
724
#define AFE_SECURE_MASK_CONN19		(0x0fdc)
725
#define AFE_SECURE_MASK_CONN20		(0x0fe0)
726
#define AFE_SECURE_MASK_CONN21		(0x0fe4)
727
#define AFE_SECURE_MASK_CONN22		(0x0fe8)
728
#define AFE_SECURE_MASK_CONN23		(0x0fec)
729
#define AFE_SECURE_MASK_CONN24		(0x0ff0)
730
#define AFE_SECURE_MASK_CONN25		(0x0ff4)
731
#define AFE_SECURE_MASK_CONN26		(0x0ff8)
732
#define AFE_SECURE_MASK_CONN27		(0x0ffc)
733

734
#define MAX_REGISTER			AFE_SECURE_MASK_CONN27
735

736
#define AFE_IRQ_STATUS_BITS		0x3ff
737

738
/* AUDIO_TOP_CON0 (0x0000) */
739
#define AUD_TCON0_PDN_TML		(1U << 27)
740
#define AUD_TCON0_PDN_DAC_PREDIS	(1U << 26)
741
#define AUD_TCON0_PDN_DAC		(1U << 25)
742
#define AUD_TCON0_PDN_ADC		(1U << 24)
743
#define AUD_TCON0_PDN_TDM_IN		(1U << 23)
744
#define AUD_TCON0_PDN_TDM_OUT		(1U << 22)
745
#define AUD_TCON0_PDN_SPDIF		(1U << 21)
746
#define AUD_TCON0_PDN_APLL_TUNER	(1U << 19)
747
#define AUD_TCON0_PDN_APLL2_TUNER	(1U << 18)
748
#define AUD_TCON0_PDN_INTDIR		(1U << 15)
749
#define AUD_TCON0_PDN_24M		(1U << 9)
750
#define AUD_TCON0_PDN_22M		(1U << 8)
751
#define AUD_TCON0_PDN_I2S_IN		(1U << 6)
752
#define AUD_TCON0_PDN_AFE		(1U << 2)
753

754
/* AUDIO_TOP_CON1 (0x0004) */
755
#define AUD_TCON1_PDN_TDM_ASRC		(1U << 15)
756
#define AUD_TCON1_PDN_GENERAL2_ASRC	(1U << 14)
757
#define AUD_TCON1_PDN_GENERAL1_ASRC	(1U << 13)
758
#define AUD_TCON1_PDN_CONNSYS_I2S_ASRC	(1U << 12)
759
#define AUD_TCON1_PDN_DMIC3_ADC		(1U << 11)
760
#define AUD_TCON1_PDN_DMIC2_ADC		(1U << 10)
761
#define AUD_TCON1_PDN_DMIC1_ADC		(1U << 9)
762
#define AUD_TCON1_PDN_DMIC0_ADC		(1U << 8)
763
#define AUD_TCON1_PDN_I2S4_BCLK		(1U << 7)
764
#define AUD_TCON1_PDN_I2S3_BCLK		(1U << 6)
765
#define AUD_TCON1_PDN_I2S2_BCLK		(1U << 5)
766
#define AUD_TCON1_PDN_I2S1_BCLK		(1U << 4)
767

768
/* AUDIO_TOP_CON3 (0x000C) */
769
#define AUD_TCON3_HDMI_BCK_INV		(1U << 3)
770

771
/* AFE_I2S_CON (0x0018) */
772
#define AFE_I2S_CON_PHASE_SHIFT_FIX	(1U << 31)
773
#define AFE_I2S_CON_FROM_IO_MUX		(1U << 28)
774
#define AFE_I2S_CON_LOW_JITTER_CLK	(1U << 12)
775
#define AFE_I2S_CON_RATE_MASK		GENMASK(11, 8)
776
#define AFE_I2S_CON_FORMAT_I2S		(1U << 3)
777
#define AFE_I2S_CON_SRC_SLAVE		(1U << 2)
778

779
/* AFE_ASRC_2CH_CON0 */
780
#define ONE_HEART	(1U << 31)
781
#define CHSET_STR_CLR	(1U << 4)
782
#define COEFF_SRAM_CTRL	(1U << 1)
783
#define ASM_ON		(1U << 0)
784

785
/* CON2 */
786
#define O16BIT		(1U << 19)
787
#define CLR_IIR_HISTORY	(1U << 17)
788
#define IS_MONO		(1U << 16)
789
#define IIR_EN		(1U << 11)
790
#define IIR_STAGE_MASK	GENMASK(10, 8)
791

792
/* CON5 */
793
#define CALI_CYCLE_MASK	GENMASK(31, 16)
794
#define CALI_64_CYCLE	FIELD_PREP(CALI_CYCLE_MASK, 0x3F)
795
#define CALI_96_CYCLE	FIELD_PREP(CALI_CYCLE_MASK, 0x5F)
796
#define CALI_441_CYCLE	FIELD_PREP(CALI_CYCLE_MASK, 0x1B8)
797

798
#define CALI_AUTORST	(1U << 15)
799
#define AUTO_TUNE_FREQ5	(1U << 12)
800
#define COMP_FREQ_RES	(1U << 11)
801

802
#define CALI_SEL_MASK	GENMASK(9, 8)
803
#define CALI_SEL_00	FIELD_PREP(CALI_SEL_MASK, 0)
804
#define CALI_SEL_01	FIELD_PREP(CALI_SEL_MASK, 1)
805

806
#define CALI_BP_DGL		(1U << 7) /* Bypass the deglitch circuit */
807
#define AUTO_TUNE_FREQ4		(1U << 3)
808
#define CALI_AUTO_RESTART	(1U << 2)
809
#define CALI_USE_FREQ_OUT	(1U << 1)
810
#define CALI_ON			(1U << 0)
811

812
#define AFE_I2S_CON_WLEN_32BIT		(1U << 1)
813
#define AFE_I2S_CON_EN			(1U << 0)
814

815
#define AFE_CONN3_I03_O03_S		(1U << 3)
816
#define AFE_CONN4_I04_O04_S		(1U << 4)
817
#define AFE_CONN4_I03_O04_S		(1U << 3)
818

819
/* AFE_I2S_CON1 (0x0034) */
820
#define AFE_I2S_CON1_I2S2_TO_PAD	(1U << 18)
821
#define AFE_I2S_CON1_TDMOUT_TO_PAD	(0 << 18)
822
#define AFE_I2S_CON1_RATE		GENMASK(11, 8)
823
#define AFE_I2S_CON1_FORMAT_I2S		(1U << 3)
824
#define AFE_I2S_CON1_WLEN_32BIT		(1U << 1)
825
#define AFE_I2S_CON1_EN			(1U << 0)
826

827
/* AFE_I2S_CON2 (0x0038) */
828
#define AFE_I2S_CON2_LOW_JITTER_CLK	(1U << 12)
829
#define AFE_I2S_CON2_RATE		GENMASK(11, 8)
830
#define AFE_I2S_CON2_FORMAT_I2S		(1U << 3)
831
#define AFE_I2S_CON2_WLEN_32BIT		(1U << 1)
832
#define AFE_I2S_CON2_EN			(1U << 0)
833

834
/* AFE_I2S_CON3 (0x004C) */
835
#define AFE_I2S_CON3_LOW_JITTER_CLK	(1U << 12)
836
#define AFE_I2S_CON3_RATE		GENMASK(11, 8)
837
#define AFE_I2S_CON3_FORMAT_I2S		(1U << 3)
838
#define AFE_I2S_CON3_WLEN_32BIT		(1U << 1)
839
#define AFE_I2S_CON3_EN			(1U << 0)
840

841
/* AFE_ADDA_DL_SRC2_CON0 (0x0108) */
842
#define AFE_ADDA_DL_SAMPLING_RATE	GENMASK(31, 28)
843
#define AFE_ADDA_DL_8X_UPSAMPLE		GENMASK(25, 24)
844
#define AFE_ADDA_DL_MUTE_OFF_CH1	(1U << 12)
845
#define AFE_ADDA_DL_MUTE_OFF_CH2	(1U << 11)
846
#define AFE_ADDA_DL_VOICE_DATA		(1U << 5)
847
#define AFE_ADDA_DL_DEGRADE_GAIN	(1U << 1)
848

849
/* AFE_ADDA_UL_SRC_CON0 (0x0114) */
850
#define AFE_ADDA_UL_SAMPLING_RATE	GENMASK(19, 17)
851

852
/* AFE_ADDA_UL_DL_CON0 */
853
#define AFE_ADDA_UL_DL_ADDA_AFE_ON	(1U << 0)
854
#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON	(1U << 1)
855

856
/* AFE_APLL_TUNER_CFG (0x03f0) */
857
#define AFE_APLL_TUNER_CFG_MASK		GENMASK(15, 1)
858
#define AFE_APLL_TUNER_CFG_EN_MASK	(1U << 0)
859

860
/* AFE_APLL_TUNER_CFG1 (0x03f4) */
861
#define AFE_APLL_TUNER_CFG1_MASK	GENMASK(15, 1)
862
#define AFE_APLL_TUNER_CFG1_EN_MASK	(1U << 0)
863

864
/* PCM_INTF_CON1 (0x0550) */
865
#define PCM_INTF_CON1_EXT_MODEM		(1U << 17)
866
#define PCM_INTF_CON1_16BIT		(0 << 16)
867
#define PCM_INTF_CON1_24BIT		(1U << 16)
868
#define PCM_INTF_CON1_32BCK		(0 << 14)
869
#define PCM_INTF_CON1_64BCK		(1U << 14)
870
#define PCM_INTF_CON1_MASTER_MODE	(0 << 5)
871
#define PCM_INTF_CON1_SLAVE_MODE	(1U << 5)
872
#define PCM_INTF_CON1_FS_MASK		GENMASK(4, 3)
873
#define PCM_INTF_CON1_FS_8K		FIELD_PREP(PCM_INTF_CON1_FS_MASK, 0)
874
#define PCM_INTF_CON1_FS_16K		FIELD_PREP(PCM_INTF_CON1_FS_MASK, 1)
875
#define PCM_INTF_CON1_FS_32K		FIELD_PREP(PCM_INTF_CON1_FS_MASK, 2)
876
#define PCM_INTF_CON1_FS_48K		FIELD_PREP(PCM_INTF_CON1_FS_MASK, 3)
877
#define PCM_INTF_CON1_SYNC_LEN_MASK	GENMASK(13, 9)
878
#define PCM_INTF_CON1_SYNC_LEN(x)	FIELD_PREP(PCM_INTF_CON1_SYNC_LEN_MASK, ((x) - 1))
879
#define PCM_INTF_CON1_FORMAT_MASK	GENMASK(2, 1)
880
#define PCM_INTF_CON1_SYNC_OUT_INV	(1U << 23)
881
#define PCM_INTF_CON1_BCLK_OUT_INV	(1U << 22)
882
#define PCM_INTF_CON1_SYNC_IN_INV	(1U << 21)
883
#define PCM_INTF_CON1_BCLK_IN_INV	(1U << 20)
884
#define PCM_INTF_CON1_BYPASS_ASRC	(1U << 6)
885
#define PCM_INTF_CON1_EN		(1U << 0)
886
#define PCM_INTF_CON1_CONFIG_MASK	(0xf3fffe)
887

888
/* AFE_DMIC0_UL_SRC_CON0 (0x05b4)
889
 * AFE_DMIC1_UL_SRC_CON0 (0x0620)
890
 * AFE_DMIC2_UL_SRC_CON0 (0x0780)
891
 * AFE_DMIC3_UL_SRC_CON0 (0x07ec)
892
 */
893
#define DMIC_TOP_CON_CK_PHASE_SEL_CH1		GENMASK(29, 27)
894
#define DMIC_TOP_CON_CK_PHASE_SEL_CH2		GENMASK(26, 24)
895
#define DMIC_TOP_CON_TWO_WIRE_MODE		(1U << 23)
896
#define DMIC_TOP_CON_CH2_ON			(1U << 22)
897
#define DMIC_TOP_CON_CH1_ON			(1U << 21)
898
#define DMIC_TOP_CON_VOICE_MODE_MASK		GENMASK(19, 17)
899
#define DMIC_TOP_CON_VOICE_MODE_8K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 0)
900
#define DMIC_TOP_CON_VOICE_MODE_16K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 1)
901
#define DMIC_TOP_CON_VOICE_MODE_32K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 2)
902
#define DMIC_TOP_CON_VOICE_MODE_48K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 3)
903
#define DMIC_TOP_CON_LOW_POWER_MODE_MASK	GENMASK(15, 14)
904
#define DMIC_TOP_CON_LOW_POWER_MODE(x)		FIELD_PREP(DMIC_TOP_CON_LOW_POWER_MODE_MASK, (x))
905
#define DMIC_TOP_CON_IIR_ON			(1U << 10)
906
#define DMIC_TOP_CON_IIR_MODE			GENMASK(9, 7)
907
#define DMIC_TOP_CON_INPUT_MODE			(1U << 5)
908
#define DMIC_TOP_CON_SDM3_LEVEL_MODE		(1U << 1)
909
#define DMIC_TOP_CON_SRC_ON			(1U << 0)
910
#define DMIC_TOP_CON_SDM3_DE_SELECT		(0 << 1)
911
#define DMIC_TOP_CON_CONFIG_MASK		(0x3f8ed7a6)
912

913
/* AFE_CONN_24BIT (0x0AA4) */
914
#define AFE_CONN_24BIT_O10		(1U << 10)
915
#define AFE_CONN_24BIT_O09		(1U << 9)
916
#define AFE_CONN_24BIT_O06		(1U << 6)
917
#define AFE_CONN_24BIT_O05		(1U << 5)
918
#define AFE_CONN_24BIT_O04		(1U << 4)
919
#define AFE_CONN_24BIT_O03		(1U << 3)
920
#define AFE_CONN_24BIT_O02		(1U << 2)
921
#define AFE_CONN_24BIT_O01		(1U << 1)
922
#define AFE_CONN_24BIT_O00		(1U << 0)
923

924
/* AFE_HD_ENGEN_ENABLE */
925
#define AFE_22M_PLL_EN		(1U << 0)
926
#define AFE_24M_PLL_EN		(1U << 1)
927

928
/* AFE_GAIN1_CON0 (0x0410) */
929
#define AFE_GAIN1_CON0_EN_MASK			GENMASK(0, 0)
930
#define AFE_GAIN1_CON0_MODE_MASK		GENMASK(7, 4)
931
#define AFE_GAIN1_CON0_SAMPLE_PER_STEP_MASK	GENMASK(15, 8)
932

933
/* AFE_GAIN1_CON1 (0x0414) */
934
#define AFE_GAIN1_CON1_MASK		GENMASK(19, 0)
935

936
/* AFE_GAIN1_CUR (0x0B78) */
937
#define AFE_GAIN1_CUR_MASK		GENMASK(19, 0)
938

939
/* AFE_CM1_CON0 (0x0e50) */
940
/* AFE_CM2_CON0 (0x0e60) */
941
#define CM_AFE_CM_CH_NUM_MASK		GENMASK(3, 0)
942
#define CM_AFE_CM_CH_NUM(x)		FIELD_PREP(CM_AFE_CM_CH_NUM_MASK, ((x) - 1))
943
#define CM_AFE_CM_ON			(1U << 4)
944
#define CM_AFE_CM_START_DATA_MASK	GENMASK(11, 8)
945

946
#define CM_AFE_CM1_VUL_SEL		(1U << 12)
947
#define CM_AFE_CM1_IN_MODE_MASK		GENMASK(19, 16)
948
#define CM_AFE_CM2_TDM_SEL		(1U << 12)
949
#define CM_AFE_CM2_CLK_SEL		(1U << 13)
950
#define CM_AFE_CM2_GASRC1_OUT_SEL	(1U << 17)
951
#define CM_AFE_CM2_GASRC2_OUT_SEL	(1U << 16)
952

953
/* AFE_CM2_CONN* */
954
#define CM2_AFE_CM2_CONN_CFG1(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG1_MASK, (x))
955
#define CM2_AFE_CM2_CONN_CFG1_MASK	GENMASK(4, 0)
956
#define CM2_AFE_CM2_CONN_CFG2(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG2_MASK, (x))
957
#define CM2_AFE_CM2_CONN_CFG2_MASK	GENMASK(9, 5)
958
#define CM2_AFE_CM2_CONN_CFG3(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG3_MASK, (x))
959
#define CM2_AFE_CM2_CONN_CFG3_MASK	GENMASK(14, 10)
960
#define CM2_AFE_CM2_CONN_CFG4(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG4_MASK, (x))
961
#define CM2_AFE_CM2_CONN_CFG4_MASK	GENMASK(19, 15)
962
#define CM2_AFE_CM2_CONN_CFG5(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG5_MASK, (x))
963
#define CM2_AFE_CM2_CONN_CFG5_MASK	GENMASK(24, 20)
964
#define CM2_AFE_CM2_CONN_CFG6(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG6_MASK, (x))
965
#define CM2_AFE_CM2_CONN_CFG6_MASK	GENMASK(29, 25)
966
#define CM2_AFE_CM2_CONN_CFG7(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG7_MASK, (x))
967
#define CM2_AFE_CM2_CONN_CFG7_MASK	GENMASK(4, 0)
968
#define CM2_AFE_CM2_CONN_CFG8(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG8_MASK, (x))
969
#define CM2_AFE_CM2_CONN_CFG8_MASK	GENMASK(9, 5)
970
#define CM2_AFE_CM2_CONN_CFG9(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG9_MASK, (x))
971
#define CM2_AFE_CM2_CONN_CFG9_MASK	GENMASK(14, 10)
972
#define CM2_AFE_CM2_CONN_CFG10(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG10_MASK, (x))
973
#define CM2_AFE_CM2_CONN_CFG10_MASK	GENMASK(19, 15)
974
#define CM2_AFE_CM2_CONN_CFG11(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG11_MASK, (x))
975
#define CM2_AFE_CM2_CONN_CFG11_MASK	GENMASK(24, 20)
976
#define CM2_AFE_CM2_CONN_CFG12(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG12_MASK, (x))
977
#define CM2_AFE_CM2_CONN_CFG12_MASK	GENMASK(29, 25)
978
#define CM2_AFE_CM2_CONN_CFG13(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG13_MASK, (x))
979
#define CM2_AFE_CM2_CONN_CFG13_MASK	GENMASK(4, 0)
980
#define CM2_AFE_CM2_CONN_CFG14(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG14_MASK, (x))
981
#define CM2_AFE_CM2_CONN_CFG14_MASK	GENMASK(9, 5)
982
#define CM2_AFE_CM2_CONN_CFG15(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG15_MASK, (x))
983
#define CM2_AFE_CM2_CONN_CFG15_MASK	GENMASK(14, 10)
984
#define CM2_AFE_CM2_CONN_CFG16(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG16_MASK, (x))
985
#define CM2_AFE_CM2_CONN_CFG16_MASK	GENMASK(19, 15)
986

987
/* AFE_CM1_CON* */
988
#define CM_AFE_CM_UPDATE_CNT1_MASK	GENMASK(15, 0)
989
#define CM_AFE_CM_UPDATE_CNT1(x)	FIELD_PREP(CM_AFE_CM_UPDATE_CNT1_MASK, (x))
990
#define CM_AFE_CM_UPDATE_CNT2_MASK	GENMASK(31, 16)
991
#define CM_AFE_CM_UPDATE_CNT2(x)	FIELD_PREP(CM_AFE_CM_UPDATE_CNT2_MASK, (x))
992

993
#endif
994

995
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