Path: blob/master/tools/testing/selftests/iommu/iommufd_utils.h
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/* SPDX-License-Identifier: GPL-2.0-only */1/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES */2#ifndef __SELFTEST_IOMMUFD_UTILS3#define __SELFTEST_IOMMUFD_UTILS45#include <unistd.h>6#include <stddef.h>7#include <sys/fcntl.h>8#include <sys/ioctl.h>9#include <stdint.h>10#include <assert.h>11#include <poll.h>1213#include "kselftest_harness.h"14#include "../../../../drivers/iommu/iommufd/iommufd_test.h"1516/* Hack to make assertions more readable */17#define _IOMMU_TEST_CMD(x) IOMMU_TEST_CMD1819/* Imported from include/asm-generic/bitops/generic-non-atomic.h */20#define BITS_PER_BYTE 821#define BITS_PER_LONG __BITS_PER_LONG22#define BIT_MASK(nr) (1UL << ((nr) % __BITS_PER_LONG))23#define BIT_WORD(nr) ((nr) / __BITS_PER_LONG)2425enum {26IOPT_PAGES_ACCOUNT_NONE = 0,27IOPT_PAGES_ACCOUNT_USER = 1,28IOPT_PAGES_ACCOUNT_MM = 2,29};3031#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))3233static inline void set_bit(unsigned int nr, unsigned long *addr)34{35unsigned long mask = BIT_MASK(nr);36unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);3738*p |= mask;39}4041static inline bool test_bit(unsigned int nr, unsigned long *addr)42{43return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)));44}4546static void *buffer;47static unsigned long BUFFER_SIZE;4849static void *mfd_buffer;50static int mfd;5152static unsigned long PAGE_SIZE;5354#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER))55#define offsetofend(TYPE, MEMBER) \56(offsetof(TYPE, MEMBER) + sizeof_field(TYPE, MEMBER))5758#define test_err_mmap(_errno, length, offset) \59EXPECT_ERRNO(_errno, (long)mmap(NULL, length, PROT_READ | PROT_WRITE, \60MAP_SHARED, self->fd, offset))6162static inline void *memfd_mmap(size_t length, int prot, int flags, int *mfd_p)63{64int mfd_flags = (flags & MAP_HUGETLB) ? MFD_HUGETLB : 0;65int mfd = memfd_create("buffer", mfd_flags);66void *buf = MAP_FAILED;6768if (mfd <= 0)69return MAP_FAILED;70if (ftruncate(mfd, length))71goto out;72*mfd_p = mfd;73buf = mmap(0, length, prot, flags, mfd, 0);74out:75if (buf == MAP_FAILED)76close(mfd);77return buf;78}7980/*81* Have the kernel check the refcount on pages. I don't know why a freshly82* mmap'd anon non-compound page starts out with a ref of 383*/84#define check_refs(_ptr, _length, _refs) \85({ \86struct iommu_test_cmd test_cmd = { \87.size = sizeof(test_cmd), \88.op = IOMMU_TEST_OP_MD_CHECK_REFS, \89.check_refs = { .length = _length, \90.uptr = (uintptr_t)(_ptr), \91.refs = _refs }, \92}; \93ASSERT_EQ(0, \94ioctl(self->fd, \95_IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_REFS), \96&test_cmd)); \97})9899static int _test_cmd_mock_domain(int fd, unsigned int ioas_id, __u32 *stdev_id,100__u32 *hwpt_id, __u32 *idev_id)101{102struct iommu_test_cmd cmd = {103.size = sizeof(cmd),104.op = IOMMU_TEST_OP_MOCK_DOMAIN,105.id = ioas_id,106.mock_domain = {},107};108int ret;109110ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);111if (ret)112return ret;113if (stdev_id)114*stdev_id = cmd.mock_domain.out_stdev_id;115assert(cmd.id != 0);116if (hwpt_id)117*hwpt_id = cmd.mock_domain.out_hwpt_id;118if (idev_id)119*idev_id = cmd.mock_domain.out_idev_id;120return 0;121}122#define test_cmd_mock_domain(ioas_id, stdev_id, hwpt_id, idev_id) \123ASSERT_EQ(0, _test_cmd_mock_domain(self->fd, ioas_id, stdev_id, \124hwpt_id, idev_id))125#define test_err_mock_domain(_errno, ioas_id, stdev_id, hwpt_id) \126EXPECT_ERRNO(_errno, _test_cmd_mock_domain(self->fd, ioas_id, \127stdev_id, hwpt_id, NULL))128129static int _test_cmd_mock_domain_flags(int fd, unsigned int ioas_id,130__u32 stdev_flags, __u32 *stdev_id,131__u32 *hwpt_id, __u32 *idev_id)132{133struct iommu_test_cmd cmd = {134.size = sizeof(cmd),135.op = IOMMU_TEST_OP_MOCK_DOMAIN_FLAGS,136.id = ioas_id,137.mock_domain_flags = { .dev_flags = stdev_flags },138};139int ret;140141ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);142if (ret)143return ret;144if (stdev_id)145*stdev_id = cmd.mock_domain_flags.out_stdev_id;146assert(cmd.id != 0);147if (hwpt_id)148*hwpt_id = cmd.mock_domain_flags.out_hwpt_id;149if (idev_id)150*idev_id = cmd.mock_domain_flags.out_idev_id;151return 0;152}153#define test_cmd_mock_domain_flags(ioas_id, flags, stdev_id, hwpt_id, idev_id) \154ASSERT_EQ(0, _test_cmd_mock_domain_flags(self->fd, ioas_id, flags, \155stdev_id, hwpt_id, idev_id))156#define test_err_mock_domain_flags(_errno, ioas_id, flags, stdev_id, hwpt_id) \157EXPECT_ERRNO(_errno, \158_test_cmd_mock_domain_flags(self->fd, ioas_id, flags, \159stdev_id, hwpt_id, NULL))160161static int _test_cmd_mock_domain_replace(int fd, __u32 stdev_id, __u32 pt_id,162__u32 *hwpt_id)163{164struct iommu_test_cmd cmd = {165.size = sizeof(cmd),166.op = IOMMU_TEST_OP_MOCK_DOMAIN_REPLACE,167.id = stdev_id,168.mock_domain_replace = {169.pt_id = pt_id,170},171};172int ret;173174ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);175if (ret)176return ret;177if (hwpt_id)178*hwpt_id = cmd.mock_domain_replace.pt_id;179return 0;180}181182#define test_cmd_mock_domain_replace(stdev_id, pt_id) \183ASSERT_EQ(0, _test_cmd_mock_domain_replace(self->fd, stdev_id, pt_id, \184NULL))185#define test_err_mock_domain_replace(_errno, stdev_id, pt_id) \186EXPECT_ERRNO(_errno, _test_cmd_mock_domain_replace(self->fd, stdev_id, \187pt_id, NULL))188189static int _test_cmd_hwpt_alloc(int fd, __u32 device_id, __u32 pt_id, __u32 ft_id,190__u32 flags, __u32 *hwpt_id, __u32 data_type,191void *data, size_t data_len)192{193struct iommu_hwpt_alloc cmd = {194.size = sizeof(cmd),195.flags = flags,196.dev_id = device_id,197.pt_id = pt_id,198.data_type = data_type,199.data_len = data_len,200.data_uptr = (uint64_t)data,201.fault_id = ft_id,202};203int ret;204205ret = ioctl(fd, IOMMU_HWPT_ALLOC, &cmd);206if (ret)207return ret;208if (hwpt_id)209*hwpt_id = cmd.out_hwpt_id;210return 0;211}212213#define test_cmd_hwpt_alloc(device_id, pt_id, flags, hwpt_id) \214ASSERT_EQ(0, _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, 0, flags, \215hwpt_id, IOMMU_HWPT_DATA_NONE, NULL, \2160))217#define test_cmd_hwpt_alloc_iommupt(device_id, pt_id, flags, iommupt_type, \218hwpt_id) \219({ \220struct iommu_hwpt_selftest user_cfg = { \221.pagetable_type = iommupt_type \222}; \223\224ASSERT_EQ(0, _test_cmd_hwpt_alloc( \225self->fd, device_id, pt_id, 0, flags, \226hwpt_id, IOMMU_HWPT_DATA_SELFTEST, \227&user_cfg, sizeof(user_cfg))); \228})229#define test_err_hwpt_alloc(_errno, device_id, pt_id, flags, hwpt_id) \230EXPECT_ERRNO(_errno, _test_cmd_hwpt_alloc( \231self->fd, device_id, pt_id, 0, flags, \232hwpt_id, IOMMU_HWPT_DATA_NONE, NULL, 0))233234#define test_cmd_hwpt_alloc_nested(device_id, pt_id, flags, hwpt_id, \235data_type, data, data_len) \236ASSERT_EQ(0, _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, 0, flags, \237hwpt_id, data_type, data, data_len))238#define test_err_hwpt_alloc_nested(_errno, device_id, pt_id, flags, hwpt_id, \239data_type, data, data_len) \240EXPECT_ERRNO(_errno, \241_test_cmd_hwpt_alloc(self->fd, device_id, pt_id, 0, flags, \242hwpt_id, data_type, data, data_len))243244#define test_cmd_hwpt_alloc_iopf(device_id, pt_id, fault_id, flags, hwpt_id, \245data_type, data, data_len) \246ASSERT_EQ(0, _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, fault_id, \247flags, hwpt_id, data_type, data, \248data_len))249#define test_err_hwpt_alloc_iopf(_errno, device_id, pt_id, fault_id, flags, \250hwpt_id, data_type, data, data_len) \251EXPECT_ERRNO(_errno, \252_test_cmd_hwpt_alloc(self->fd, device_id, pt_id, fault_id, \253flags, hwpt_id, data_type, data, \254data_len))255256#define test_cmd_hwpt_check_iotlb(hwpt_id, iotlb_id, expected) \257({ \258struct iommu_test_cmd test_cmd = { \259.size = sizeof(test_cmd), \260.op = IOMMU_TEST_OP_MD_CHECK_IOTLB, \261.id = hwpt_id, \262.check_iotlb = { \263.id = iotlb_id, \264.iotlb = expected, \265}, \266}; \267ASSERT_EQ(0, \268ioctl(self->fd, \269_IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_IOTLB), \270&test_cmd)); \271})272273#define test_cmd_hwpt_check_iotlb_all(hwpt_id, expected) \274({ \275int i; \276for (i = 0; i < MOCK_NESTED_DOMAIN_IOTLB_NUM; i++) \277test_cmd_hwpt_check_iotlb(hwpt_id, i, expected); \278})279280#define test_cmd_dev_check_cache(device_id, cache_id, expected) \281({ \282struct iommu_test_cmd test_cmd = { \283.size = sizeof(test_cmd), \284.op = IOMMU_TEST_OP_DEV_CHECK_CACHE, \285.id = device_id, \286.check_dev_cache = { \287.id = cache_id, \288.cache = expected, \289}, \290}; \291ASSERT_EQ(0, ioctl(self->fd, \292_IOMMU_TEST_CMD( \293IOMMU_TEST_OP_DEV_CHECK_CACHE), \294&test_cmd)); \295})296297#define test_cmd_dev_check_cache_all(device_id, expected) \298({ \299int c; \300for (c = 0; c < MOCK_DEV_CACHE_NUM; c++) \301test_cmd_dev_check_cache(device_id, c, expected); \302})303304static int _test_cmd_hwpt_invalidate(int fd, __u32 hwpt_id, void *reqs,305uint32_t data_type, uint32_t lreq,306uint32_t *nreqs)307{308struct iommu_hwpt_invalidate cmd = {309.size = sizeof(cmd),310.hwpt_id = hwpt_id,311.data_type = data_type,312.data_uptr = (uint64_t)reqs,313.entry_len = lreq,314.entry_num = *nreqs,315};316int rc = ioctl(fd, IOMMU_HWPT_INVALIDATE, &cmd);317*nreqs = cmd.entry_num;318return rc;319}320321#define test_cmd_hwpt_invalidate(hwpt_id, reqs, data_type, lreq, nreqs) \322({ \323ASSERT_EQ(0, \324_test_cmd_hwpt_invalidate(self->fd, hwpt_id, reqs, \325data_type, lreq, nreqs)); \326})327#define test_err_hwpt_invalidate(_errno, hwpt_id, reqs, data_type, lreq, \328nreqs) \329({ \330EXPECT_ERRNO(_errno, _test_cmd_hwpt_invalidate( \331self->fd, hwpt_id, reqs, \332data_type, lreq, nreqs)); \333})334335static int _test_cmd_viommu_invalidate(int fd, __u32 viommu_id, void *reqs,336uint32_t data_type, uint32_t lreq,337uint32_t *nreqs)338{339struct iommu_hwpt_invalidate cmd = {340.size = sizeof(cmd),341.hwpt_id = viommu_id,342.data_type = data_type,343.data_uptr = (uint64_t)reqs,344.entry_len = lreq,345.entry_num = *nreqs,346};347int rc = ioctl(fd, IOMMU_HWPT_INVALIDATE, &cmd);348*nreqs = cmd.entry_num;349return rc;350}351352#define test_cmd_viommu_invalidate(viommu, reqs, lreq, nreqs) \353({ \354ASSERT_EQ(0, \355_test_cmd_viommu_invalidate(self->fd, viommu, reqs, \356IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, \357lreq, nreqs)); \358})359#define test_err_viommu_invalidate(_errno, viommu_id, reqs, data_type, lreq, \360nreqs) \361({ \362EXPECT_ERRNO(_errno, _test_cmd_viommu_invalidate( \363self->fd, viommu_id, reqs, \364data_type, lreq, nreqs)); \365})366367static int _test_cmd_access_replace_ioas(int fd, __u32 access_id,368unsigned int ioas_id)369{370struct iommu_test_cmd cmd = {371.size = sizeof(cmd),372.op = IOMMU_TEST_OP_ACCESS_REPLACE_IOAS,373.id = access_id,374.access_replace_ioas = { .ioas_id = ioas_id },375};376int ret;377378ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);379if (ret)380return ret;381return 0;382}383#define test_cmd_access_replace_ioas(access_id, ioas_id) \384ASSERT_EQ(0, _test_cmd_access_replace_ioas(self->fd, access_id, ioas_id))385386static int _test_cmd_set_dirty_tracking(int fd, __u32 hwpt_id, bool enabled)387{388struct iommu_hwpt_set_dirty_tracking cmd = {389.size = sizeof(cmd),390.flags = enabled ? IOMMU_HWPT_DIRTY_TRACKING_ENABLE : 0,391.hwpt_id = hwpt_id,392};393int ret;394395ret = ioctl(fd, IOMMU_HWPT_SET_DIRTY_TRACKING, &cmd);396if (ret)397return -errno;398return 0;399}400#define test_cmd_set_dirty_tracking(hwpt_id, enabled) \401ASSERT_EQ(0, _test_cmd_set_dirty_tracking(self->fd, hwpt_id, enabled))402403static int _test_cmd_get_dirty_bitmap(int fd, __u32 hwpt_id, size_t length,404__u64 iova, size_t page_size,405__u64 *bitmap, __u32 flags)406{407struct iommu_hwpt_get_dirty_bitmap cmd = {408.size = sizeof(cmd),409.hwpt_id = hwpt_id,410.flags = flags,411.iova = iova,412.length = length,413.page_size = page_size,414.data = (uintptr_t)bitmap,415};416int ret;417418ret = ioctl(fd, IOMMU_HWPT_GET_DIRTY_BITMAP, &cmd);419if (ret)420return ret;421return 0;422}423424#define test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, page_size, \425bitmap, flags) \426ASSERT_EQ(0, _test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, \427page_size, bitmap, flags))428429static int _test_cmd_mock_domain_set_dirty(int fd, __u32 hwpt_id, size_t length,430__u64 iova, size_t page_size,431__u64 *bitmap, __u64 *dirty)432{433struct iommu_test_cmd cmd = {434.size = sizeof(cmd),435.op = IOMMU_TEST_OP_DIRTY,436.id = hwpt_id,437.dirty = {438.iova = iova,439.length = length,440.page_size = page_size,441.uptr = (uintptr_t)bitmap,442}443};444int ret;445446ret = ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_DIRTY), &cmd);447if (ret)448return -ret;449if (dirty)450*dirty = cmd.dirty.out_nr_dirty;451return 0;452}453454#define test_cmd_mock_domain_set_dirty(fd, hwpt_id, length, iova, page_size, \455bitmap, nr) \456ASSERT_EQ(0, \457_test_cmd_mock_domain_set_dirty(fd, hwpt_id, length, iova, \458page_size, bitmap, nr))459460static int _test_mock_dirty_bitmaps(int fd, __u32 hwpt_id, size_t length,461__u64 iova, size_t page_size,462size_t pte_page_size, __u64 *bitmap,463__u64 nbits, __u32 flags,464struct __test_metadata *_metadata)465{466unsigned long npte = pte_page_size / page_size, pteset = 2 * npte;467unsigned long j, i, nr = nbits / pteset ?: 1;468unsigned long bitmap_size = DIV_ROUND_UP(nbits, BITS_PER_BYTE);469__u64 out_dirty = 0;470471/* Mark all even bits as dirty in the mock domain */472memset(bitmap, 0, bitmap_size);473for (i = 0; i < nbits; i += pteset)474set_bit(i, (unsigned long *)bitmap);475476test_cmd_mock_domain_set_dirty(fd, hwpt_id, length, iova, page_size,477bitmap, &out_dirty);478ASSERT_EQ(nr, out_dirty);479480/* Expect all even bits as dirty in the user bitmap */481memset(bitmap, 0, bitmap_size);482test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, page_size, bitmap,483flags);484/* Beware ASSERT_EQ() is two statements -- braces are not redundant! */485for (i = 0; i < nbits; i += pteset) {486for (j = 0; j < pteset; j++) {487ASSERT_EQ(j < npte,488test_bit(i + j, (unsigned long *)bitmap));489}490ASSERT_EQ(!(i % pteset), test_bit(i, (unsigned long *)bitmap));491}492493memset(bitmap, 0, bitmap_size);494test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, page_size, bitmap,495flags);496497/* It as read already -- expect all zeroes */498for (i = 0; i < nbits; i += pteset) {499for (j = 0; j < pteset; j++) {500ASSERT_EQ(501(j < npte) &&502(flags &503IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR),504test_bit(i + j, (unsigned long *)bitmap));505}506}507508return 0;509}510#define test_mock_dirty_bitmaps(hwpt_id, length, iova, page_size, pte_size,\511bitmap, bitmap_size, flags, _metadata) \512ASSERT_EQ(0, _test_mock_dirty_bitmaps(self->fd, hwpt_id, length, iova, \513page_size, pte_size, bitmap, \514bitmap_size, flags, _metadata))515516static int _test_cmd_create_access(int fd, unsigned int ioas_id,517__u32 *access_id, unsigned int flags)518{519struct iommu_test_cmd cmd = {520.size = sizeof(cmd),521.op = IOMMU_TEST_OP_CREATE_ACCESS,522.id = ioas_id,523.create_access = { .flags = flags },524};525int ret;526527ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);528if (ret)529return ret;530*access_id = cmd.create_access.out_access_fd;531return 0;532}533#define test_cmd_create_access(ioas_id, access_id, flags) \534ASSERT_EQ(0, _test_cmd_create_access(self->fd, ioas_id, access_id, \535flags))536537static int _test_cmd_destroy_access(unsigned int access_id)538{539return close(access_id);540}541#define test_cmd_destroy_access(access_id) \542ASSERT_EQ(0, _test_cmd_destroy_access(access_id))543544static int _test_cmd_destroy_access_pages(int fd, unsigned int access_id,545unsigned int access_pages_id)546{547struct iommu_test_cmd cmd = {548.size = sizeof(cmd),549.op = IOMMU_TEST_OP_DESTROY_ACCESS_PAGES,550.id = access_id,551.destroy_access_pages = { .access_pages_id = access_pages_id },552};553return ioctl(fd, IOMMU_TEST_CMD, &cmd);554}555#define test_cmd_destroy_access_pages(access_id, access_pages_id) \556ASSERT_EQ(0, _test_cmd_destroy_access_pages(self->fd, access_id, \557access_pages_id))558#define test_err_destroy_access_pages(_errno, access_id, access_pages_id) \559EXPECT_ERRNO(_errno, _test_cmd_destroy_access_pages( \560self->fd, access_id, access_pages_id))561562static int _test_cmd_get_dmabuf(int fd, size_t len, int *out_fd)563{564struct iommu_test_cmd cmd = {565.size = sizeof(cmd),566.op = IOMMU_TEST_OP_DMABUF_GET,567.dmabuf_get = { .length = len, .open_flags = O_CLOEXEC },568};569570*out_fd = ioctl(fd, IOMMU_TEST_CMD, &cmd);571if (*out_fd < 0)572return -1;573return 0;574}575#define test_cmd_get_dmabuf(len, out_fd) \576ASSERT_EQ(0, _test_cmd_get_dmabuf(self->fd, len, out_fd))577578static int _test_cmd_revoke_dmabuf(int fd, int dmabuf_fd, bool revoked)579{580struct iommu_test_cmd cmd = {581.size = sizeof(cmd),582.op = IOMMU_TEST_OP_DMABUF_REVOKE,583.dmabuf_revoke = { .dmabuf_fd = dmabuf_fd, .revoked = revoked },584};585int ret;586587ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);588if (ret < 0)589return -1;590return 0;591}592#define test_cmd_revoke_dmabuf(dmabuf_fd, revoke) \593ASSERT_EQ(0, _test_cmd_revoke_dmabuf(self->fd, dmabuf_fd, revoke))594595static int _test_ioctl_destroy(int fd, unsigned int id)596{597struct iommu_destroy cmd = {598.size = sizeof(cmd),599.id = id,600};601return ioctl(fd, IOMMU_DESTROY, &cmd);602}603#define test_ioctl_destroy(id) ASSERT_EQ(0, _test_ioctl_destroy(self->fd, id))604605static int _test_ioctl_ioas_alloc(int fd, __u32 *id)606{607struct iommu_ioas_alloc cmd = {608.size = sizeof(cmd),609};610int ret;611612ret = ioctl(fd, IOMMU_IOAS_ALLOC, &cmd);613if (ret)614return ret;615*id = cmd.out_ioas_id;616return 0;617}618#define test_ioctl_ioas_alloc(id) \619({ \620ASSERT_EQ(0, _test_ioctl_ioas_alloc(self->fd, id)); \621ASSERT_NE(0, *(id)); \622})623624static int _test_ioctl_ioas_map(int fd, unsigned int ioas_id, void *buffer,625size_t length, __u64 *iova, unsigned int flags)626{627struct iommu_ioas_map cmd = {628.size = sizeof(cmd),629.flags = flags,630.ioas_id = ioas_id,631.user_va = (uintptr_t)buffer,632.length = length,633};634int ret;635636if (flags & IOMMU_IOAS_MAP_FIXED_IOVA)637cmd.iova = *iova;638639ret = ioctl(fd, IOMMU_IOAS_MAP, &cmd);640*iova = cmd.iova;641return ret;642}643#define test_ioctl_ioas_map(buffer, length, iova_p) \644ASSERT_EQ(0, _test_ioctl_ioas_map(self->fd, self->ioas_id, buffer, \645length, iova_p, \646IOMMU_IOAS_MAP_WRITEABLE | \647IOMMU_IOAS_MAP_READABLE))648649#define test_err_ioctl_ioas_map(_errno, buffer, length, iova_p) \650EXPECT_ERRNO(_errno, \651_test_ioctl_ioas_map(self->fd, self->ioas_id, buffer, \652length, iova_p, \653IOMMU_IOAS_MAP_WRITEABLE | \654IOMMU_IOAS_MAP_READABLE))655656#define test_ioctl_ioas_map_id(ioas_id, buffer, length, iova_p) \657ASSERT_EQ(0, _test_ioctl_ioas_map(self->fd, ioas_id, buffer, length, \658iova_p, \659IOMMU_IOAS_MAP_WRITEABLE | \660IOMMU_IOAS_MAP_READABLE))661662#define test_ioctl_ioas_map_fixed(buffer, length, iova) \663({ \664__u64 __iova = iova; \665ASSERT_EQ(0, _test_ioctl_ioas_map( \666self->fd, self->ioas_id, buffer, length, \667&__iova, \668IOMMU_IOAS_MAP_FIXED_IOVA | \669IOMMU_IOAS_MAP_WRITEABLE | \670IOMMU_IOAS_MAP_READABLE)); \671})672673#define test_ioctl_ioas_map_fixed_id(ioas_id, buffer, length, iova) \674({ \675__u64 __iova = iova; \676ASSERT_EQ(0, \677_test_ioctl_ioas_map( \678self->fd, ioas_id, buffer, length, &__iova, \679IOMMU_IOAS_MAP_FIXED_IOVA | \680IOMMU_IOAS_MAP_WRITEABLE | \681IOMMU_IOAS_MAP_READABLE)); \682})683684#define test_err_ioctl_ioas_map_fixed(_errno, buffer, length, iova) \685({ \686__u64 __iova = iova; \687EXPECT_ERRNO(_errno, \688_test_ioctl_ioas_map( \689self->fd, self->ioas_id, buffer, length, \690&__iova, \691IOMMU_IOAS_MAP_FIXED_IOVA | \692IOMMU_IOAS_MAP_WRITEABLE | \693IOMMU_IOAS_MAP_READABLE)); \694})695696static int _test_ioctl_ioas_unmap(int fd, unsigned int ioas_id, uint64_t iova,697size_t length, uint64_t *out_len)698{699struct iommu_ioas_unmap cmd = {700.size = sizeof(cmd),701.ioas_id = ioas_id,702.iova = iova,703.length = length,704};705int ret;706707ret = ioctl(fd, IOMMU_IOAS_UNMAP, &cmd);708if (out_len)709*out_len = cmd.length;710return ret;711}712#define test_ioctl_ioas_unmap(iova, length) \713ASSERT_EQ(0, _test_ioctl_ioas_unmap(self->fd, self->ioas_id, iova, \714length, NULL))715716#define test_ioctl_ioas_unmap_id(ioas_id, iova, length) \717ASSERT_EQ(0, _test_ioctl_ioas_unmap(self->fd, ioas_id, iova, length, \718NULL))719720#define test_err_ioctl_ioas_unmap(_errno, iova, length) \721EXPECT_ERRNO(_errno, _test_ioctl_ioas_unmap(self->fd, self->ioas_id, \722iova, length, NULL))723724static int _test_ioctl_ioas_map_file(int fd, unsigned int ioas_id, int mfd,725size_t start, size_t length, __u64 *iova,726unsigned int flags)727{728struct iommu_ioas_map_file cmd = {729.size = sizeof(cmd),730.flags = flags,731.ioas_id = ioas_id,732.fd = mfd,733.start = start,734.length = length,735};736int ret;737738if (flags & IOMMU_IOAS_MAP_FIXED_IOVA)739cmd.iova = *iova;740741ret = ioctl(fd, IOMMU_IOAS_MAP_FILE, &cmd);742*iova = cmd.iova;743return ret;744}745746#define test_ioctl_ioas_map_file(mfd, start, length, iova_p) \747ASSERT_EQ(0, \748_test_ioctl_ioas_map_file( \749self->fd, self->ioas_id, mfd, start, length, iova_p, \750IOMMU_IOAS_MAP_WRITEABLE | IOMMU_IOAS_MAP_READABLE))751752#define test_err_ioctl_ioas_map_file(_errno, mfd, start, length, iova_p) \753EXPECT_ERRNO( \754_errno, \755_test_ioctl_ioas_map_file( \756self->fd, self->ioas_id, mfd, start, length, iova_p, \757IOMMU_IOAS_MAP_WRITEABLE | IOMMU_IOAS_MAP_READABLE))758759#define test_ioctl_ioas_map_id_file(ioas_id, mfd, start, length, iova_p) \760ASSERT_EQ(0, \761_test_ioctl_ioas_map_file( \762self->fd, ioas_id, mfd, start, length, iova_p, \763IOMMU_IOAS_MAP_WRITEABLE | IOMMU_IOAS_MAP_READABLE))764765#define test_ioctl_ioas_map_fixed_file(mfd, start, length, iova) \766({ \767__u64 __iova = iova; \768ASSERT_EQ(0, _test_ioctl_ioas_map_file( \769self->fd, self->ioas_id, mfd, start, \770length, &__iova, \771IOMMU_IOAS_MAP_FIXED_IOVA | \772IOMMU_IOAS_MAP_WRITEABLE | \773IOMMU_IOAS_MAP_READABLE)); \774})775776static int _test_ioctl_set_temp_memory_limit(int fd, unsigned int limit)777{778struct iommu_test_cmd memlimit_cmd = {779.size = sizeof(memlimit_cmd),780.op = IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT,781.memory_limit = { .limit = limit },782};783784return ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT),785&memlimit_cmd);786}787788#define test_ioctl_set_temp_memory_limit(limit) \789ASSERT_EQ(0, _test_ioctl_set_temp_memory_limit(self->fd, limit))790791#define test_ioctl_set_default_memory_limit() \792test_ioctl_set_temp_memory_limit(65536)793794static void teardown_iommufd(int fd, struct __test_metadata *_metadata)795{796struct iommu_test_cmd test_cmd = {797.size = sizeof(test_cmd),798.op = IOMMU_TEST_OP_MD_CHECK_REFS,799.check_refs = { .length = BUFFER_SIZE,800.uptr = (uintptr_t)buffer },801};802803if (fd == -1)804return;805806EXPECT_EQ(0, close(fd));807808fd = open("/dev/iommu", O_RDWR);809EXPECT_NE(-1, fd);810EXPECT_EQ(0, ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_REFS),811&test_cmd));812EXPECT_EQ(0, close(fd));813}814815#define EXPECT_ERRNO(expected_errno, cmd) \816({ \817ASSERT_EQ(-1, cmd); \818EXPECT_EQ(expected_errno, errno); \819})820821#endif822823/* @data can be NULL */824static int _test_cmd_get_hw_info(int fd, __u32 device_id, __u32 data_type,825void *data, size_t data_len,826uint32_t *capabilities, uint8_t *max_pasid)827{828struct iommu_test_hw_info *info = (struct iommu_test_hw_info *)data;829struct iommu_hw_info cmd = {830.size = sizeof(cmd),831.dev_id = device_id,832.data_len = data_len,833.in_data_type = data_type,834.data_uptr = (uint64_t)data,835.out_capabilities = 0,836};837int ret;838839if (data_type != IOMMU_HW_INFO_TYPE_DEFAULT)840cmd.flags |= IOMMU_HW_INFO_FLAG_INPUT_TYPE;841842ret = ioctl(fd, IOMMU_GET_HW_INFO, &cmd);843if (ret)844return ret;845846assert(cmd.out_data_type == IOMMU_HW_INFO_TYPE_SELFTEST);847848/*849* The struct iommu_test_hw_info should be the one defined850* by the current kernel.851*/852assert(cmd.data_len == sizeof(struct iommu_test_hw_info));853854/*855* Trailing bytes should be 0 if user buffer is larger than856* the data that kernel reports.857*/858if (data_len > cmd.data_len) {859char *ptr = (char *)(data + cmd.data_len);860int idx = 0;861862while (idx < data_len - cmd.data_len) {863assert(!*(ptr + idx));864idx++;865}866}867868if (info) {869if (data_len >= offsetofend(struct iommu_test_hw_info, test_reg))870assert(info->test_reg == IOMMU_HW_INFO_SELFTEST_REGVAL);871if (data_len >= offsetofend(struct iommu_test_hw_info, flags))872assert(!info->flags);873}874875if (max_pasid)876*max_pasid = cmd.out_max_pasid_log2;877878if (capabilities)879*capabilities = cmd.out_capabilities;880881return 0;882}883884#define test_cmd_get_hw_info(device_id, data_type, data, data_len) \885ASSERT_EQ(0, _test_cmd_get_hw_info(self->fd, device_id, data_type, \886data, data_len, NULL, NULL))887888#define test_err_get_hw_info(_errno, device_id, data_type, data, data_len) \889EXPECT_ERRNO(_errno, \890_test_cmd_get_hw_info(self->fd, device_id, data_type, \891data, data_len, NULL, NULL))892893#define test_cmd_get_hw_capabilities(device_id, caps) \894ASSERT_EQ(0, _test_cmd_get_hw_info(self->fd, device_id, \895IOMMU_HW_INFO_TYPE_DEFAULT, NULL, \8960, &caps, NULL))897898#define test_cmd_get_hw_info_pasid(device_id, max_pasid) \899ASSERT_EQ(0, _test_cmd_get_hw_info(self->fd, device_id, \900IOMMU_HW_INFO_TYPE_DEFAULT, NULL, \9010, NULL, max_pasid))902903static int _test_ioctl_fault_alloc(int fd, __u32 *fault_id, __u32 *fault_fd)904{905struct iommu_fault_alloc cmd = {906.size = sizeof(cmd),907};908int ret;909910ret = ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd);911if (ret)912return ret;913*fault_id = cmd.out_fault_id;914*fault_fd = cmd.out_fault_fd;915return 0;916}917918#define test_ioctl_fault_alloc(fault_id, fault_fd) \919({ \920ASSERT_EQ(0, _test_ioctl_fault_alloc(self->fd, fault_id, \921fault_fd)); \922ASSERT_NE(0, *(fault_id)); \923ASSERT_NE(0, *(fault_fd)); \924})925926static int _test_cmd_trigger_iopf(int fd, __u32 device_id, __u32 pasid,927__u32 fault_fd)928{929struct iommu_test_cmd trigger_iopf_cmd = {930.size = sizeof(trigger_iopf_cmd),931.op = IOMMU_TEST_OP_TRIGGER_IOPF,932.trigger_iopf = {933.dev_id = device_id,934.pasid = pasid,935.grpid = 0x2,936.perm = IOMMU_PGFAULT_PERM_READ | IOMMU_PGFAULT_PERM_WRITE,937.addr = 0xdeadbeaf,938},939};940struct iommu_hwpt_page_response response = {941.code = IOMMUFD_PAGE_RESP_SUCCESS,942};943struct iommu_hwpt_pgfault fault = {};944ssize_t bytes;945int ret;946947ret = ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_TRIGGER_IOPF), &trigger_iopf_cmd);948if (ret)949return ret;950951bytes = read(fault_fd, &fault, sizeof(fault));952if (bytes <= 0)953return -EIO;954955response.cookie = fault.cookie;956957bytes = write(fault_fd, &response, sizeof(response));958if (bytes <= 0)959return -EIO;960961return 0;962}963964#define test_cmd_trigger_iopf(device_id, fault_fd) \965ASSERT_EQ(0, _test_cmd_trigger_iopf(self->fd, device_id, 0x1, fault_fd))966#define test_cmd_trigger_iopf_pasid(device_id, pasid, fault_fd) \967ASSERT_EQ(0, _test_cmd_trigger_iopf(self->fd, device_id, \968pasid, fault_fd))969970static int _test_cmd_viommu_alloc(int fd, __u32 device_id, __u32 hwpt_id,971__u32 flags, __u32 type, void *data,972__u32 data_len, __u32 *viommu_id)973{974struct iommu_viommu_alloc cmd = {975.size = sizeof(cmd),976.flags = flags,977.type = type,978.dev_id = device_id,979.hwpt_id = hwpt_id,980.data_uptr = (uint64_t)data,981.data_len = data_len,982};983int ret;984985ret = ioctl(fd, IOMMU_VIOMMU_ALLOC, &cmd);986if (ret)987return ret;988if (viommu_id)989*viommu_id = cmd.out_viommu_id;990return 0;991}992993#define test_cmd_viommu_alloc(device_id, hwpt_id, type, data, data_len, \994viommu_id) \995ASSERT_EQ(0, _test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, 0, \996type, data, data_len, viommu_id))997#define test_err_viommu_alloc(_errno, device_id, hwpt_id, type, data, \998data_len, viommu_id) \999EXPECT_ERRNO(_errno, \1000_test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, 0, \1001type, data, data_len, viommu_id))10021003static int _test_cmd_vdevice_alloc(int fd, __u32 viommu_id, __u32 idev_id,1004__u64 virt_id, __u32 *vdev_id)1005{1006struct iommu_vdevice_alloc cmd = {1007.size = sizeof(cmd),1008.dev_id = idev_id,1009.viommu_id = viommu_id,1010.virt_id = virt_id,1011};1012int ret;10131014ret = ioctl(fd, IOMMU_VDEVICE_ALLOC, &cmd);1015if (ret)1016return ret;1017if (vdev_id)1018*vdev_id = cmd.out_vdevice_id;1019return 0;1020}10211022#define test_cmd_vdevice_alloc(viommu_id, idev_id, virt_id, vdev_id) \1023ASSERT_EQ(0, _test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, \1024virt_id, vdev_id))1025#define test_err_vdevice_alloc(_errno, viommu_id, idev_id, virt_id, vdev_id) \1026EXPECT_ERRNO(_errno, \1027_test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, \1028virt_id, vdev_id))10291030static int _test_cmd_hw_queue_alloc(int fd, __u32 viommu_id, __u32 type,1031__u32 idx, __u64 base_addr, __u64 length,1032__u32 *hw_queue_id)1033{1034struct iommu_hw_queue_alloc cmd = {1035.size = sizeof(cmd),1036.viommu_id = viommu_id,1037.type = type,1038.index = idx,1039.nesting_parent_iova = base_addr,1040.length = length,1041};1042int ret;10431044ret = ioctl(fd, IOMMU_HW_QUEUE_ALLOC, &cmd);1045if (ret)1046return ret;1047if (hw_queue_id)1048*hw_queue_id = cmd.out_hw_queue_id;1049return 0;1050}10511052#define test_cmd_hw_queue_alloc(viommu_id, type, idx, base_addr, len, out_qid) \1053ASSERT_EQ(0, _test_cmd_hw_queue_alloc(self->fd, viommu_id, type, idx, \1054base_addr, len, out_qid))1055#define test_err_hw_queue_alloc(_errno, viommu_id, type, idx, base_addr, len, \1056out_qid) \1057EXPECT_ERRNO(_errno, \1058_test_cmd_hw_queue_alloc(self->fd, viommu_id, type, idx, \1059base_addr, len, out_qid))10601061static int _test_cmd_veventq_alloc(int fd, __u32 viommu_id, __u32 type,1062__u32 *veventq_id, __u32 *veventq_fd)1063{1064struct iommu_veventq_alloc cmd = {1065.size = sizeof(cmd),1066.type = type,1067.veventq_depth = 2,1068.viommu_id = viommu_id,1069};1070int ret;10711072ret = ioctl(fd, IOMMU_VEVENTQ_ALLOC, &cmd);1073if (ret)1074return ret;1075if (veventq_id)1076*veventq_id = cmd.out_veventq_id;1077if (veventq_fd)1078*veventq_fd = cmd.out_veventq_fd;1079return 0;1080}10811082#define test_cmd_veventq_alloc(viommu_id, type, veventq_id, veventq_fd) \1083ASSERT_EQ(0, _test_cmd_veventq_alloc(self->fd, viommu_id, type, \1084veventq_id, veventq_fd))1085#define test_err_veventq_alloc(_errno, viommu_id, type, veventq_id, \1086veventq_fd) \1087EXPECT_ERRNO(_errno, \1088_test_cmd_veventq_alloc(self->fd, viommu_id, type, \1089veventq_id, veventq_fd))10901091static int _test_cmd_trigger_vevents(int fd, __u32 dev_id, __u32 nvevents)1092{1093struct iommu_test_cmd trigger_vevent_cmd = {1094.size = sizeof(trigger_vevent_cmd),1095.op = IOMMU_TEST_OP_TRIGGER_VEVENT,1096.trigger_vevent = {1097.dev_id = dev_id,1098},1099};11001101while (nvevents--) {1102if (ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_TRIGGER_VEVENT),1103&trigger_vevent_cmd))1104return -1;1105}1106return 0;1107}11081109#define test_cmd_trigger_vevents(dev_id, nvevents) \1110ASSERT_EQ(0, _test_cmd_trigger_vevents(self->fd, dev_id, nvevents))11111112static int _test_cmd_read_vevents(int fd, __u32 event_fd, __u32 nvevents,1113__u32 virt_id, int *prev_seq)1114{1115struct pollfd pollfd = { .fd = event_fd, .events = POLLIN };1116struct iommu_viommu_event_selftest *event;1117struct iommufd_vevent_header *hdr;1118ssize_t bytes;1119void *data;1120int ret, i;11211122ret = poll(&pollfd, 1, 1000);1123if (ret < 0)1124return -1;11251126data = calloc(nvevents, sizeof(*hdr) + sizeof(*event));1127if (!data) {1128errno = ENOMEM;1129return -1;1130}11311132bytes = read(event_fd, data,1133nvevents * (sizeof(*hdr) + sizeof(*event)));1134if (bytes <= 0) {1135errno = EFAULT;1136ret = -1;1137goto out_free;1138}11391140for (i = 0; i < nvevents; i++) {1141hdr = data + i * (sizeof(*hdr) + sizeof(*event));11421143if (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS ||1144hdr->sequence - *prev_seq > 1) {1145*prev_seq = hdr->sequence;1146errno = EOVERFLOW;1147ret = -1;1148goto out_free;1149}1150*prev_seq = hdr->sequence;1151event = data + sizeof(*hdr);1152if (event->virt_id != virt_id) {1153errno = EINVAL;1154ret = -1;1155goto out_free;1156}1157}11581159ret = 0;1160out_free:1161free(data);1162return ret;1163}11641165#define test_cmd_read_vevents(event_fd, nvevents, virt_id, prev_seq) \1166ASSERT_EQ(0, _test_cmd_read_vevents(self->fd, event_fd, nvevents, \1167virt_id, prev_seq))1168#define test_err_read_vevents(_errno, event_fd, nvevents, virt_id, prev_seq) \1169EXPECT_ERRNO(_errno, \1170_test_cmd_read_vevents(self->fd, event_fd, nvevents, \1171virt_id, prev_seq))11721173static int _test_cmd_pasid_attach(int fd, __u32 stdev_id, __u32 pasid,1174__u32 pt_id)1175{1176struct iommu_test_cmd test_attach = {1177.size = sizeof(test_attach),1178.op = IOMMU_TEST_OP_PASID_ATTACH,1179.id = stdev_id,1180.pasid_attach = {1181.pasid = pasid,1182.pt_id = pt_id,1183},1184};11851186return ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_PASID_ATTACH),1187&test_attach);1188}11891190#define test_cmd_pasid_attach(pasid, hwpt_id) \1191ASSERT_EQ(0, _test_cmd_pasid_attach(self->fd, self->stdev_id, \1192pasid, hwpt_id))11931194#define test_err_pasid_attach(_errno, pasid, hwpt_id) \1195EXPECT_ERRNO(_errno, \1196_test_cmd_pasid_attach(self->fd, self->stdev_id, \1197pasid, hwpt_id))11981199static int _test_cmd_pasid_replace(int fd, __u32 stdev_id, __u32 pasid,1200__u32 pt_id)1201{1202struct iommu_test_cmd test_replace = {1203.size = sizeof(test_replace),1204.op = IOMMU_TEST_OP_PASID_REPLACE,1205.id = stdev_id,1206.pasid_replace = {1207.pasid = pasid,1208.pt_id = pt_id,1209},1210};12111212return ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_PASID_REPLACE),1213&test_replace);1214}12151216#define test_cmd_pasid_replace(pasid, hwpt_id) \1217ASSERT_EQ(0, _test_cmd_pasid_replace(self->fd, self->stdev_id, \1218pasid, hwpt_id))12191220#define test_err_pasid_replace(_errno, pasid, hwpt_id) \1221EXPECT_ERRNO(_errno, \1222_test_cmd_pasid_replace(self->fd, self->stdev_id, \1223pasid, hwpt_id))12241225static int _test_cmd_pasid_detach(int fd, __u32 stdev_id, __u32 pasid)1226{1227struct iommu_test_cmd test_detach = {1228.size = sizeof(test_detach),1229.op = IOMMU_TEST_OP_PASID_DETACH,1230.id = stdev_id,1231.pasid_detach = {1232.pasid = pasid,1233},1234};12351236return ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_PASID_DETACH),1237&test_detach);1238}12391240#define test_cmd_pasid_detach(pasid) \1241ASSERT_EQ(0, _test_cmd_pasid_detach(self->fd, self->stdev_id, pasid))12421243static int test_cmd_pasid_check_hwpt(int fd, __u32 stdev_id, __u32 pasid,1244__u32 hwpt_id)1245{1246struct iommu_test_cmd test_pasid_check = {1247.size = sizeof(test_pasid_check),1248.op = IOMMU_TEST_OP_PASID_CHECK_HWPT,1249.id = stdev_id,1250.pasid_check = {1251.pasid = pasid,1252.hwpt_id = hwpt_id,1253},1254};12551256return ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_PASID_CHECK_HWPT),1257&test_pasid_check);1258}125912601261