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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/tools/testing/selftests/kvm/x86/smm_test.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018, Red Hat, Inc.
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*
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* Tests for SMM.
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*/
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <sys/ioctl.h>
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#include "test_util.h"
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#include "kvm_util.h"
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#include "vmx.h"
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#include "svm_util.h"
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#define SMRAM_SIZE 65536
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#define SMRAM_MEMSLOT ((1 << 16) | 1)
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#define SMRAM_PAGES (SMRAM_SIZE / PAGE_SIZE)
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#define SMRAM_GPA 0x1000000
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#define SMRAM_STAGE 0xfe
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#define STR(x) #x
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#define XSTR(s) STR(s)
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#define SYNC_PORT 0xe
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#define DONE 0xff
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/*
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* This is compiled as normal 64-bit code, however, SMI handler is executed
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* in real-address mode. To stay simple we're limiting ourselves to a mode
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* independent subset of asm here.
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* SMI handler always report back fixed stage SMRAM_STAGE.
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*/
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uint8_t smi_handler[] = {
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0xb0, SMRAM_STAGE, /* mov $SMRAM_STAGE, %al */
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0xe4, SYNC_PORT, /* in $SYNC_PORT, %al */
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0x0f, 0xaa, /* rsm */
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};
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static inline void sync_with_host(uint64_t phase)
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{
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asm volatile("in $" XSTR(SYNC_PORT)", %%al \n"
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: "+a" (phase));
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}
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static void self_smi(void)
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{
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x2apic_write_reg(APIC_ICR,
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APIC_DEST_SELF | APIC_INT_ASSERT | APIC_DM_SMI);
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}
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static void l2_guest_code(void)
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{
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sync_with_host(8);
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sync_with_host(10);
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vmcall();
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}
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static void guest_code(void *arg)
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{
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#define L2_GUEST_STACK_SIZE 64
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unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
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uint64_t apicbase = rdmsr(MSR_IA32_APICBASE);
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struct svm_test_data *svm = arg;
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struct vmx_pages *vmx_pages = arg;
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sync_with_host(1);
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wrmsr(MSR_IA32_APICBASE, apicbase | X2APIC_ENABLE);
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sync_with_host(2);
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self_smi();
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sync_with_host(4);
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if (arg) {
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if (this_cpu_has(X86_FEATURE_SVM)) {
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generic_svm_setup(svm, l2_guest_code,
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&l2_guest_stack[L2_GUEST_STACK_SIZE]);
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} else {
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GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages));
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GUEST_ASSERT(load_vmcs(vmx_pages));
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prepare_vmcs(vmx_pages, l2_guest_code,
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&l2_guest_stack[L2_GUEST_STACK_SIZE]);
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}
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sync_with_host(5);
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self_smi();
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sync_with_host(7);
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if (this_cpu_has(X86_FEATURE_SVM)) {
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run_guest(svm->vmcb, svm->vmcb_gpa);
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run_guest(svm->vmcb, svm->vmcb_gpa);
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} else {
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vmlaunch();
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vmresume();
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}
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/* Stages 8-11 are eaten by SMM (SMRAM_STAGE reported instead) */
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sync_with_host(12);
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}
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sync_with_host(DONE);
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}
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void inject_smi(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_events events;
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vcpu_events_get(vcpu, &events);
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events.smi.pending = 1;
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events.flags |= KVM_VCPUEVENT_VALID_SMM;
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vcpu_events_set(vcpu, &events);
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}
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int main(int argc, char *argv[])
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{
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vm_vaddr_t nested_gva = 0;
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struct kvm_vcpu *vcpu;
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struct kvm_regs regs;
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struct kvm_vm *vm;
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struct kvm_x86_state *state;
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int stage, stage_reported;
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TEST_REQUIRE(kvm_has_cap(KVM_CAP_X86_SMM));
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/* Create VM */
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vm = vm_create_with_one_vcpu(&vcpu, guest_code);
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vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, SMRAM_GPA,
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SMRAM_MEMSLOT, SMRAM_PAGES, 0);
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TEST_ASSERT(vm_phy_pages_alloc(vm, SMRAM_PAGES, SMRAM_GPA, SMRAM_MEMSLOT)
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== SMRAM_GPA, "could not allocate guest physical addresses?");
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memset(addr_gpa2hva(vm, SMRAM_GPA), 0x0, SMRAM_SIZE);
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memcpy(addr_gpa2hva(vm, SMRAM_GPA) + 0x8000, smi_handler,
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sizeof(smi_handler));
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vcpu_set_msr(vcpu, MSR_IA32_SMBASE, SMRAM_GPA);
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if (kvm_has_cap(KVM_CAP_NESTED_STATE)) {
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if (kvm_cpu_has(X86_FEATURE_SVM))
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vcpu_alloc_svm(vm, &nested_gva);
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else if (kvm_cpu_has(X86_FEATURE_VMX))
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vcpu_alloc_vmx(vm, &nested_gva);
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}
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if (!nested_gva)
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pr_info("will skip SMM test with VMX enabled\n");
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vcpu_args_set(vcpu, 1, nested_gva);
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for (stage = 1;; stage++) {
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vcpu_run(vcpu);
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TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
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memset(&regs, 0, sizeof(regs));
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vcpu_regs_get(vcpu, &regs);
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stage_reported = regs.rax & 0xff;
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if (stage_reported == DONE)
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goto done;
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TEST_ASSERT(stage_reported == stage ||
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stage_reported == SMRAM_STAGE,
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"Unexpected stage: #%x, got %x",
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stage, stage_reported);
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/*
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* Enter SMM during L2 execution and check that we correctly
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* return from it. Do not perform save/restore while in SMM yet.
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*/
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if (stage == 8) {
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inject_smi(vcpu);
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continue;
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}
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/*
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* Perform save/restore while the guest is in SMM triggered
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* during L2 execution.
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*/
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if (stage == 10)
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inject_smi(vcpu);
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state = vcpu_save_state(vcpu);
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kvm_vm_release(vm);
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vcpu = vm_recreate_with_one_vcpu(vm);
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vcpu_load_state(vcpu, state);
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kvm_x86_state_cleanup(state);
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}
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done:
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kvm_vm_free(vm);
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}
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