CoCalc -- UopEnum.h

GitHub Repository: alexbevi/BizHawk
Path: blob/master/BizHawk.Emulation.Cores/CPUs/MOS 6502X/6502XXX/UopEnum.h
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// AUTOGENERATED
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#ifndef UOPENUM_H
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#define UOPENUM_H
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enum Uop {
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	Uop_Unsupported, 
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	Uop_Fetch1, 
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	Uop_Fetch1_Real, 
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	Uop_Fetch2, 
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	Uop_Fetch3, 
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	Uop_FetchDummy, 
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	Uop_NOP, 
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	Uop_JSR, 
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	Uop_IncPC, 
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	Uop_Abs_WRITE_STA, 
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	Uop_Abs_WRITE_STX, 
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	Uop_Abs_WRITE_STY, 
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	Uop_Abs_WRITE_SAX, 
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	Uop_Abs_READ_BIT, 
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	Uop_Abs_READ_LDA, 
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	Uop_Abs_READ_LDY, 
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	Uop_Abs_READ_ORA, 
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	Uop_Abs_READ_LDX, 
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	Uop_Abs_READ_CMP, 
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	Uop_Abs_READ_ADC, 
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	Uop_Abs_READ_CPX, 
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	Uop_Abs_READ_SBC, 
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	Uop_Abs_READ_AND, 
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	Uop_Abs_READ_EOR, 
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	Uop_Abs_READ_CPY, 
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	Uop_Abs_READ_NOP, 
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	Uop_Abs_READ_LAX, 
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	Uop_Abs_RMW_Stage4, 
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	Uop_Abs_RMW_Stage6, 
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	Uop_Abs_RMW_Stage5_INC, 
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	Uop_Abs_RMW_Stage5_DEC, 
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	Uop_Abs_RMW_Stage5_LSR, 
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	Uop_Abs_RMW_Stage5_ROL, 
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	Uop_Abs_RMW_Stage5_ASL, 
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	Uop_Abs_RMW_Stage5_ROR, 
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	Uop_Abs_RMW_Stage5_SLO, 
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	Uop_Abs_RMW_Stage5_RLA, 
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	Uop_Abs_RMW_Stage5_SRE, 
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	Uop_Abs_RMW_Stage5_RRA, 
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	Uop_Abs_RMW_Stage5_DCP, 
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	Uop_Abs_RMW_Stage5_ISC, 
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	Uop_JMP_abs, 
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	Uop_ZpIdx_Stage3_X, 
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	Uop_ZpIdx_Stage3_Y, 
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	Uop_ZpIdx_RMW_Stage4, 
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	Uop_ZpIdx_RMW_Stage6, 
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	Uop_ZP_WRITE_STA, 
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	Uop_ZP_WRITE_STX, 
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	Uop_ZP_WRITE_STY, 
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	Uop_ZP_WRITE_SAX, 
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	Uop_ZP_RMW_Stage3, 
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	Uop_ZP_RMW_Stage5, 
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	Uop_ZP_RMW_DEC, 
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	Uop_ZP_RMW_INC, 
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	Uop_ZP_RMW_ASL, 
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	Uop_ZP_RMW_LSR, 
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	Uop_ZP_RMW_ROR, 
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	Uop_ZP_RMW_ROL, 
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	Uop_ZP_RMW_SLO, 
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	Uop_ZP_RMW_RLA, 
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	Uop_ZP_RMW_SRE, 
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	Uop_ZP_RMW_RRA, 
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	Uop_ZP_RMW_DCP, 
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	Uop_ZP_RMW_ISC, 
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	Uop_ZP_READ_EOR, 
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	Uop_ZP_READ_BIT, 
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	Uop_ZP_READ_ORA, 
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	Uop_ZP_READ_LDA, 
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	Uop_ZP_READ_LDY, 
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	Uop_ZP_READ_LDX, 
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	Uop_ZP_READ_CPX, 
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	Uop_ZP_READ_SBC, 
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	Uop_ZP_READ_CPY, 
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	Uop_ZP_READ_NOP, 
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	Uop_ZP_READ_ADC, 
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	Uop_ZP_READ_AND, 
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	Uop_ZP_READ_CMP, 
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	Uop_ZP_READ_LAX, 
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	Uop_IdxInd_Stage3, 
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	Uop_IdxInd_Stage4, 
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	Uop_IdxInd_Stage5, 
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	Uop_IdxInd_Stage6_READ_ORA, 
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	Uop_IdxInd_Stage6_READ_SBC, 
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	Uop_IdxInd_Stage6_READ_LDA, 
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	Uop_IdxInd_Stage6_READ_EOR, 
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	Uop_IdxInd_Stage6_READ_CMP, 
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	Uop_IdxInd_Stage6_READ_ADC, 
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	Uop_IdxInd_Stage6_READ_AND, 
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	Uop_IdxInd_Stage6_READ_LAX, 
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	Uop_IdxInd_Stage6_WRITE_STA, 
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	Uop_IdxInd_Stage6_WRITE_SAX, 
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	Uop_IdxInd_Stage6_RMW, 
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	Uop_IdxInd_Stage7_RMW_SLO, 
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	Uop_IdxInd_Stage7_RMW_RLA, 
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	Uop_IdxInd_Stage7_RMW_SRE, 
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	Uop_IdxInd_Stage7_RMW_RRA, 
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	Uop_IdxInd_Stage7_RMW_ISC, 
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	Uop_IdxInd_Stage7_RMW_DCP, 
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	Uop_IdxInd_Stage8_RMW, 
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	Uop_AbsIdx_Stage3_X, 
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	Uop_AbsIdx_Stage3_Y, 
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	Uop_AbsIdx_Stage4, 
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	Uop_AbsIdx_WRITE_Stage5_STA, 
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	Uop_AbsIdx_WRITE_Stage5_SHY, 
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	Uop_AbsIdx_WRITE_Stage5_SHX, 
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	Uop_AbsIdx_WRITE_Stage5_ERROR, 
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	Uop_AbsIdx_READ_Stage4, 
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	Uop_AbsIdx_READ_Stage5_LDA, 
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	Uop_AbsIdx_READ_Stage5_CMP, 
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	Uop_AbsIdx_READ_Stage5_SBC, 
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	Uop_AbsIdx_READ_Stage5_ADC, 
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	Uop_AbsIdx_READ_Stage5_EOR, 
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	Uop_AbsIdx_READ_Stage5_LDX, 
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	Uop_AbsIdx_READ_Stage5_AND, 
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	Uop_AbsIdx_READ_Stage5_ORA, 
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	Uop_AbsIdx_READ_Stage5_LDY, 
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	Uop_AbsIdx_READ_Stage5_NOP, 
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	Uop_AbsIdx_READ_Stage5_LAX, 
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	Uop_AbsIdx_READ_Stage5_ERROR, 
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	Uop_AbsIdx_RMW_Stage5, 
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	Uop_AbsIdx_RMW_Stage7, 
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	Uop_AbsIdx_RMW_Stage6_ROR, 
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	Uop_AbsIdx_RMW_Stage6_DEC, 
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	Uop_AbsIdx_RMW_Stage6_INC, 
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	Uop_AbsIdx_RMW_Stage6_ASL, 
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	Uop_AbsIdx_RMW_Stage6_LSR, 
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	Uop_AbsIdx_RMW_Stage6_ROL, 
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	Uop_AbsIdx_RMW_Stage6_SLO, 
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	Uop_AbsIdx_RMW_Stage6_RLA, 
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	Uop_AbsIdx_RMW_Stage6_SRE, 
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	Uop_AbsIdx_RMW_Stage6_RRA, 
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	Uop_AbsIdx_RMW_Stage6_DCP, 
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	Uop_AbsIdx_RMW_Stage6_ISC, 
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	Uop_IncS, 
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	Uop_DecS, 
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	Uop_PushPCL, 
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	Uop_PushPCH, 
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	Uop_PushP, 
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	Uop_PullP, 
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	Uop_PullPCL, 
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	Uop_PullPCH_NoInc, 
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	Uop_PushA, 
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	Uop_PullA_NoInc, 
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	Uop_PullP_NoInc, 
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	Uop_PushP_BRK, 
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	Uop_PushP_NMI, 
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	Uop_PushP_IRQ, 
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	Uop_PushP_Reset, 
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	Uop_PushDummy, 
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	Uop_FetchPCLVector, 
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	Uop_FetchPCHVector, 
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	Uop_Imp_ASL_A, 
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	Uop_Imp_ROL_A, 
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	Uop_Imp_ROR_A, 
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	Uop_Imp_LSR_A, 
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	Uop_Imp_SEC, 
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	Uop_Imp_CLI, 
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	Uop_Imp_SEI, 
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	Uop_Imp_CLD, 
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	Uop_Imp_CLC, 
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	Uop_Imp_CLV, 
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	Uop_Imp_SED, 
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	Uop_Imp_INY, 
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	Uop_Imp_DEY, 
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	Uop_Imp_INX, 
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	Uop_Imp_DEX, 
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	Uop_Imp_TSX, 
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	Uop_Imp_TXS, 
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	Uop_Imp_TAX, 
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	Uop_Imp_TAY, 
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	Uop_Imp_TYA, 
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	Uop_Imp_TXA, 
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	Uop_Imm_CMP, 
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	Uop_Imm_ADC, 
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	Uop_Imm_AND, 
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	Uop_Imm_SBC, 
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	Uop_Imm_ORA, 
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	Uop_Imm_EOR, 
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	Uop_Imm_CPY, 
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	Uop_Imm_CPX, 
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	Uop_Imm_ANC, 
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	Uop_Imm_ASR, 
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	Uop_Imm_ARR, 
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	Uop_Imm_LXA, 
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	Uop_Imm_AXS, 
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	Uop_Imm_LDA, 
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	Uop_Imm_LDX, 
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	Uop_Imm_LDY, 
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	Uop_Imm_Unsupported, 
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	Uop_NZ_X, 
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	Uop_NZ_Y, 
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	Uop_NZ_A, 
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	Uop_RelBranch_Stage2_BNE, 
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	Uop_RelBranch_Stage2_BPL, 
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	Uop_RelBranch_Stage2_BCC, 
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	Uop_RelBranch_Stage2_BCS, 
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	Uop_RelBranch_Stage2_BEQ, 
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	Uop_RelBranch_Stage2_BMI, 
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	Uop_RelBranch_Stage2_BVC, 
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	Uop_RelBranch_Stage2_BVS, 
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	Uop_RelBranch_Stage2, 
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	Uop_RelBranch_Stage3, 
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	Uop_RelBranch_Stage4, 
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	Uop__Eor, 
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	Uop__Bit, 
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	Uop__Cpx, 
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	Uop__Cpy, 
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	Uop__Cmp, 
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	Uop__Adc, 
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	Uop__Sbc, 
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	Uop__Ora, 
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	Uop__And, 
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	Uop__Anc, 
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	Uop__Asr, 
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	Uop__Arr, 
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	Uop__Lxa, 
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	Uop__Axs, 
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	Uop_AbsInd_JMP_Stage4, 
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	Uop_AbsInd_JMP_Stage5, 
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	Uop_IndIdx_Stage3, 
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	Uop_IndIdx_Stage4, 
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	Uop_IndIdx_READ_Stage5, 
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	Uop_IndIdx_WRITE_Stage5, 
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	Uop_IndIdx_WRITE_Stage6_STA, 
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	Uop_IndIdx_WRITE_Stage6_SHA, 
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	Uop_IndIdx_READ_Stage6_LDA, 
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	Uop_IndIdx_READ_Stage6_CMP, 
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	Uop_IndIdx_READ_Stage6_ORA, 
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	Uop_IndIdx_READ_Stage6_SBC, 
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	Uop_IndIdx_READ_Stage6_ADC, 
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	Uop_IndIdx_READ_Stage6_AND, 
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	Uop_IndIdx_READ_Stage6_EOR, 
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	Uop_IndIdx_READ_Stage6_LAX, 
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	Uop_IndIdx_RMW_Stage5, 
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	Uop_IndIdx_RMW_Stage6, 
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	Uop_IndIdx_RMW_Stage7_SLO, 
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	Uop_IndIdx_RMW_Stage7_RLA, 
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	Uop_IndIdx_RMW_Stage7_SRE, 
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	Uop_IndIdx_RMW_Stage7_RRA, 
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	Uop_IndIdx_RMW_Stage7_ISC, 
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	Uop_IndIdx_RMW_Stage7_DCP, 
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	Uop_IndIdx_RMW_Stage8, 
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	Uop_End, 
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	Uop_End_ISpecial, 
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	Uop_End_BranchSpecial, 
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	Uop_End_SuppressInterrupt, 
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};
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#endif // UOPENUM_H
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