#include "shared.h"1#include "eeprom_93c.h"2#include "eq.h"3456extern struct7{8uint8 enabled;9uint8 status;10uint8 *rom;11uint8 *ram;12uint16 regs[13];13uint16 old[4];14uint16 data[4];15uint32 addr[4];16} action_replay;1718typedef struct19{20uint8 address_bits; // number of bits needed to address memory: 7, 8 or 16 //21uint16 size_mask; // depends on the max size of the memory (in bytes) //22uint16 pagewrite_mask; // depends on the maximal number of bytes that can be written in a single write cycle //23uint32 sda_in_adr; // 68000 memory address mapped to SDA_IN //24uint32 sda_out_adr; // 68000 memory address mapped to SDA_OUT //25uint32 scl_adr; // 68000 memory address mapped to SCL //26uint8 sda_in_bit; // bit offset for SDA_IN //27uint8 sda_out_bit; // bit offset for SDA_OUT //28uint8 scl_bit; // bit offset for SCL //29} T_CONFIG_I2C;3031typedef enum32{33STAND_BY = 0,34WAIT_STOP,35GET_SLAVE_ADR,36GET_WORD_ADR_7BITS,37GET_WORD_ADR_HIGH,38GET_WORD_ADR_LOW,39WRITE_DATA,40READ_DATA41} T_STATE_I2C;4243typedef struct44{45uint8 sda; // current /SDA line state //46uint8 scl; // current /SCL line state //47uint8 old_sda; // previous /SDA line state //48uint8 old_scl; // previous /SCL line state //49uint8 cycles; // current operation cycle number (0-9) //50uint8 rw; // operation type (1:READ, 0:WRITE) //51uint16 slave_mask; // device address (shifted by the memory address width)//52uint16 word_address; // memory address //53T_STATE_I2C state; // current operation state //54T_CONFIG_I2C config; // EEPROM characteristics for this game //55} T_EEPROM_I2C;5657extern T_EEPROM_I2C eeprom_i2c;5859typedef enum60{61STANDBY,62GET_OPCODE_,//63GET_ADDRESS,64WRITE_BYTE,65READ_BYTE66} T_STATE_SPI;6768typedef struct69{70uint8 cs; // !CS line state //71uint8 clk; // SCLK line state //72uint8 out; // SO line state //73uint8 status; // status register //74uint8 opcode; // 8-bit opcode //75uint8 buffer; // 8-bit data buffer //76uint16 addr; // 16-bit address //77uint32 cycles; // current operation cycle //78T_STATE_SPI state; // current operation state //79} T_EEPROM_SPI;8081extern T_EEPROM_SPI spi_eeprom;8283extern struct84{85uint8 enabled;86uint8 *rom;87uint16 regs[0x20];88uint16 old[6];89uint16 data[6];90uint32 addr[6];91} ggenie;9293extern struct94{95uint8 State;96uint8 Counter;97} activator[2];9899extern uint8 pad_index;100101extern struct102{103uint8 State;104uint8 Port;105} lightgun;106107extern struct108{109uint8 State;110uint8 Counter;111uint8 Wait;112uint8 Port;113} mouse;114115extern struct116{117uint8 State;118} paddle[2];119120extern struct121{122uint8 State;123uint8 Counter;124} sportspad[2];125126extern struct127{128uint8 State;129uint8 Counter;130uint8 Table[12];131} teamplayer[2];132133extern struct134{135uint8 axis;136uint8 busy;137} tablet;138139extern struct140{141uint8 State;142uint8 Counter;143uint8 Latency;144} xe_a1p[2];145146typedef struct147{148// Configuration //149int PreAmp[4][2]; // stereo channels pre-amplification ratio (%) //150int NoiseFeedback;151int SRWidth;152153// PSG registers: //154int Registers[8]; // Tone, vol x4 //155int LatchedRegister;156int NoiseShiftRegister;157int NoiseFreq; // Noise channel signal generator frequency //158159// Output calculation variables //160int ToneFreqVals[4]; // Frequency register values (counters) //161int ToneFreqPos[4]; // Frequency channel flip-flops //162int Channel[4][2]; // current amplitude of each (stereo) channel //163int ChanOut[4][2]; // current output value of each (stereo) channel //164165// Internal M-clock counter //166unsigned long clocks;167168} SN76489_Context;169170extern SN76489_Context SN76489;171172extern int fm_buffer[1080 * 2];173extern int fm_last[2];174extern int *fm_ptr;175176// Cycle-accurate FM samples //177extern uint32 fm_cycles_ratio;178extern uint32 fm_cycles_start;179extern uint32 fm_cycles_count;180181// YM chip function pointers //182extern void (*YM_Reset)(void);183extern void (*YM_Update)(int *buffer, int length);184extern void (*YM_Write)(unsigned int a, unsigned int v);185186typedef struct187{188UINT32 ar; // attack rate: AR<<2 //189UINT32 dr; // decay rate: DR<<2 //190UINT32 rr; // release rate:RR<<2 //191UINT8 KSR; // key scale rate //192UINT8 ksl; // keyscale level //193UINT8 ksr; // key scale rate: kcode>>KSR //194UINT8 mul; // multiple: mul_tab[ML] //195196// Phase Generator //197UINT32 phase; // frequency counter //198UINT32 freq; // frequency counter step //199UINT8 fb_shift; // feedback shift value //200INT32 op1_out[2]; // slot1 output for feedback //201202// Envelope Generator //203UINT8 eg_type; // percussive/nonpercussive mode //204UINT8 state; // phase type //205UINT32 TL; // total level: TL << 2 //206INT32 TLL; // adjusted now TL //207INT32 volume; // envelope counter //208UINT32 sl; // sustain level: sl_tab[SL] //209210UINT8 eg_sh_dp; // (dump state) //211UINT8 eg_sel_dp; // (dump state) //212UINT8 eg_sh_ar; // (attack state) //213UINT8 eg_sel_ar; // (attack state) //214UINT8 eg_sh_dr; // (decay state) //215UINT8 eg_sel_dr; // (decay state) //216UINT8 eg_sh_rr; // (release state for non-perc.) //217UINT8 eg_sel_rr; // (release state for non-perc.) //218UINT8 eg_sh_rs; // (release state for perc.mode) //219UINT8 eg_sel_rs; // (release state for perc.mode) //220221UINT32 key; // 0 = KEY OFF, >0 = KEY ON //222223// LFO //224UINT32 AMmask; // LFO Amplitude Modulation enable mask //225UINT8 vib; // LFO Phase Modulation enable flag (active high)//226227// waveform select //228unsigned int wavetable;229} YM2413_OPLL_SLOT;230231typedef struct232{233YM2413_OPLL_SLOT SLOT[2];234235// phase generator state //236UINT32 block_fnum; // block+fnum //237UINT32 fc; // Freq. freqement base //238UINT32 ksl_base; // KeyScaleLevel Base step //239UINT8 kcode; // key code (for key scaling) //240UINT8 sus; // sus on/off (release speed in percussive mode) //241} YM2413_OPLL_CH;242243// chip state //244typedef struct {245YM2413_OPLL_CH P_CH[9]; // OPLL chips have 9 channels //246UINT8 instvol_r[9]; // instrument/volume (or volume/volume in percussive mode) //247248UINT32 eg_cnt; // global envelope generator counter //249UINT32 eg_timer; // global envelope generator counter works at frequency = chipclock/72 //250UINT32 eg_timer_add; // step of eg_timer //251UINT32 eg_timer_overflow; // envelope generator timer overlfows every 1 sample (on real chip) //252253UINT8 rhythm; // Rhythm mode //254255// LFO //256UINT32 lfo_am_cnt;257UINT32 lfo_am_inc;258UINT32 lfo_pm_cnt;259UINT32 lfo_pm_inc;260261UINT32 noise_rng; // 23 bit noise shift register //262UINT32 noise_p; // current noise 'phase' //263UINT32 noise_f; // current noise period //264265266// instrument settings //267//268//0-user instrument269//1-15 - fixed instruments270//16 -bass drum settings271//17,18 - other percussion instruments272//273UINT8 inst_tab[19][8];274275UINT32 fn_tab[1024]; // fnumber->increment counter //276277UINT8 address; // address register //278UINT8 status; // status flag //279280double clock; // master clock (Hz) //281int rate; // sampling rate (Hz) //282} YM2413;283284extern YM2413 ym2413;285286// struct describing a single operator (SLOT) //287typedef struct288{289INT32 *DT; // detune :dt_tab[DT] //290UINT8 KSR; // key scale rate :3-KSR //291UINT32 ar; // attack rate //292UINT32 d1r; // decay rate //293UINT32 d2r; // sustain rate //294UINT32 rr; // release rate //295UINT8 ksr; // key scale rate :kcode>>(3-KSR) //296UINT32 mul; // multiple :ML_TABLE[ML] //297298// Phase Generator //299UINT32 phase; // phase counter //300INT32 Incr; // phase step //301302// Envelope Generator //303UINT8 state; // phase type //304UINT32 tl; // total level: TL << 3 //305INT32 volume; // envelope counter //306UINT32 sl; // sustain level:sl_table[SL] //307UINT32 vol_out; // current output from EG circuit (without AM from LFO) //308309UINT8 eg_sh_ar; // (attack state) //310UINT8 eg_sel_ar; // (attack state) //311UINT8 eg_sh_d1r; // (decay state) //312UINT8 eg_sel_d1r; // (decay state) //313UINT8 eg_sh_d2r; // (sustain state) //314UINT8 eg_sel_d2r; // (sustain state) //315UINT8 eg_sh_rr; // (release state) //316UINT8 eg_sel_rr; // (release state) //317318UINT8 ssg; // SSG-EG waveform //319UINT8 ssgn; // SSG-EG negated output //320321UINT8 key; // 0=last key was KEY OFF, 1=KEY ON //322323// LFO //324UINT32 AMmask; // AM enable flag //325326} FM_SLOT;327328typedef struct329{330FM_SLOT SLOT[4]; // four SLOTs (operators) //331332UINT8 ALGO; // algorithm //333UINT8 FB; // feedback shift //334INT32 op1_out[2]; // op1 output for feedback //335336INT32 *connect1; // SLOT1 output pointer //337INT32 *connect3; // SLOT3 output pointer //338INT32 *connect2; // SLOT2 output pointer //339INT32 *connect4; // SLOT4 output pointer //340341INT32 *mem_connect; // where to put the delayed sample (MEM) //342INT32 mem_value; // delayed sample (MEM) value //343344INT32 pms; // channel PMS //345UINT8 ams; // channel AMS //346347UINT32 fc; // fnum,blk //348UINT8 kcode; // key code //349UINT32 block_fnum; // blk/fnum value (for LFO PM calculations) //350} FM_CH;351352353typedef struct354{355UINT16 address; // address register //356UINT8 status; // status flag //357UINT32 mode; // mode CSM / 3SLOT //358UINT8 fn_h; // freq latch //359INT32 TA; // timer a value //360INT32 TAL; // timer a base //361INT32 TAC; // timer a counter //362INT32 TB; // timer b value //363INT32 TBL; // timer b base //364INT32 TBC; // timer b counter //365INT32 dt_tab[8][32]; // DeTune table //366367} FM_ST;368369370// OPN unit //371372373// OPN 3slot struct //374typedef struct375{376UINT32 fc[3]; // fnum3,blk3: calculated //377UINT8 fn_h; // freq3 latch //378UINT8 kcode[3]; // key code //379UINT32 block_fnum[3]; // current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) //380UINT8 key_csm; // CSM mode Key-ON flag //381382} FM_3SLOT;383384// OPN/A/B common state //385typedef struct386{387FM_ST ST; // general state //388FM_3SLOT SL3; // 3 slot mode state //389unsigned int pan[6*2]; // fm channels output masks (0xffffffff = enable) //390391// EG //392UINT32 eg_cnt; // global envelope generator counter //393UINT32 eg_timer; // global envelope generator counter works at frequency = chipclock/144/3 //394395// LFO //396UINT8 lfo_cnt; // current LFO phase (out of 128) //397UINT32 lfo_timer; // current LFO phase runs at LFO frequency //398UINT32 lfo_timer_overflow; // LFO timer overflows every N samples (depends on LFO frequency) //399UINT32 LFO_AM; // current LFO AM step //400UINT32 LFO_PM; // current LFO PM step //401402} FM_OPN;403404// YM2612 chip //405typedef struct406{407FM_CH CH[6]; // channel state //408UINT8 dacen; // DAC mode //409INT32 dacout; // DAC output //410FM_OPN OPN; // OPN state //411412} YM2612;413414extern YM2612 ym2612;415416// current chip state //417extern INT32 m2,c1,c2; // Phase Modulation input for operators 2,3,4 //418extern INT32 mem; // one sample delay memory //419extern INT32 out_fm[8]; // outputs of working channels //420extern UINT32 bitmask; // working channels output bitmasking (DAC quantization) //421422extern uint8 tmss[4]; // TMSS security register //423424extern uint8 rom_region;425426extern uint8 pause_b;427extern EQSTATE eq;428extern int16 llp,rrp;429430431432#define Z(a) memset((a), 0, sizeof(*(a)))433#define Y(a) memset((a), 0, sizeof((a)))434435void zap(void)436{437Z(&config);438Z(&eeprom_93c);439440Z(&ext);441Y(boot_rom);442Y(work_ram);443Y(zram);444Z(&zbank);445Z(&zstate);446Z(&pico_current);447Z(&input);448memset(old_system, -1, sizeof(old_system));449Y(io_reg);450Z(®ion_code);451Z(&rominfo);452Z(&romtype);453Z(&m68k);454Z(&s68k);455456Y(zbank_memory_map);457458Z(&sram); // NB: sram.sram is not allocated459460Z(&svp);461462Z(&bitmap);463Z(&snd);464465Z(&mcycles_vdp);466467Z(&system_hw);468Z(&system_bios);469Z(&system_clock);470471Y(reg);472Y(sat);473Y(vram);474Y(cram);475Y(vsram);476Z(&hint_pending);477Z(&vint_pending);478Z(&status);479Z(&dma_length);480481Z(&ntab);482Z(&ntbb);483Z(&ntwb);484Z(&satb);485Z(&hscb);486Y(bg_name_dirty);487Y(bg_name_list);488Z(&bg_list_index);489Z(&hscroll_mask);490Z(&playfield_shift);491Z(&playfield_col_mask);492Z(&playfield_row_mask);493Z(&odd_frame);494Z(&im2_flag);495Z(&interlaced);496Z(&vdp_pal);497Z(&v_counter);498Z(&vc_max);499Z(&vscroll);500Z(&lines_per_frame);501Z(&max_sprite_pixels);502Z(&fifo_write_cnt);503Z(&fifo_slots);504Z(&hvc_latch);505Z(&hctab);506507Z(&vdp_68k_data_w);508Z(&vdp_z80_data_w);509Z(&vdp_68k_data_r);510Z(&vdp_z80_data_r);511512Z(&spr_col);513514Z(&Z80);515516Y(z80_readmap);517Y(z80_writemap);518519Z(&z80_writemem);520Z(&z80_readmem);521Z(&z80_writeport);522Z(&z80_readport);523524//=======525526Z(&action_replay);527528Z(&eeprom_i2c);529Z(&spi_eeprom);530531Z(&ggenie);532533Y(activator);534535Y(gamepad);536537Z(&pad_index);538539540Z(&lightgun);541542Z(&mouse);543544Y(paddle);545546Y(sportspad);547548Y(teamplayer);549550Z(&tablet);551552Y(xe_a1p);553554Z(&SN76489);555556Y(fm_buffer);557Y(fm_last);558Z(&fm_ptr);559560Z(&fm_cycles_ratio);561Z(&fm_cycles_start);562Z(&fm_cycles_count);563564Z(&YM_Reset);565Z(&YM_Update);566Z(&YM_Write);567568Z(&ym2413);569570Z(&ym2612);571572Z(&m2);573Z(&c1);574Z(&c2);575Z(&mem);576Y(out_fm);577Z(&bitmask);578579Y(tmss);580581Z(&rom_region);582583Z(&pause_b);584Z(&eq);585Z(&llp);586Z(&rrp);587}588589590591