CoCalc -- cpu.cpp

GitHub Repository: alexbevi/BizHawk
Path: blob/master/libmeteor/source/cpu.cpp
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// Meteor - A Nintendo Gameboy Advance emulator
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// Copyright (C) 2009-2011 Philippe Daouadi
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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#include "ameteor/cpu.hpp"
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#include "ameteor/bios.hpp"
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#include "globals.hpp"
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#include "cpu_globals.hpp"
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#include "ameteor.hpp"
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#include "debug.hpp"
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#include <cstring>
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namespace AMeteor
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{
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	Cpu::Cpu ()
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	{
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		Reset();
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	}
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34
	void Cpu::Reset ()
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	{
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		std::memset(&m_st, 0, sizeof(m_st));
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		R(15) = 0x00000004;
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		m_st.icpsr.mode = M_SVC;
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		m_st.icpsr.fiq_d = true;
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		m_st.icpsr.irq_d = true;
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	}
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	void Cpu::SoftReset ()
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	{
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		std::memset(&m_st, 0, sizeof(m_st));
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		R(13) = 0x03007F00;
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		R(15) = 0x08000004;
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		m_st.irq_r[0] = 0x03007FA0; // R13
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		m_st.svc_r[0] = 0x03007FE0; // R13
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		m_st.icpsr.mode = 0x1F;
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		m_st.icpsr.fiq_d = true;
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	}
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	void Cpu::UpdateICpsr ()
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	{
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		m_st.icpsr.mode       = m_st.cpsr.b.mode;
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		m_st.icpsr.irq_d      = m_st.cpsr.b.irq_d;
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		m_st.icpsr.fiq_d      = m_st.cpsr.b.fiq_d;
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		m_st.icpsr.thumb      = m_st.cpsr.b.thumb;
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		m_st.icpsr.s_overflow = m_st.cpsr.b.s_overflow;
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		m_st.icpsr.f_overflow = m_st.cpsr.b.f_overflow;
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		m_st.icpsr.f_carry    = m_st.cpsr.b.f_carry;
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		m_st.icpsr.f_zero     = m_st.cpsr.b.f_zero;
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		m_st.icpsr.f_sign     = m_st.cpsr.b.f_sign;
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	}
66

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	void Cpu::UpdateCpsr ()
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	{
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		m_st.cpsr.b.mode       = m_st.icpsr.mode;
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		m_st.cpsr.b.irq_d      = m_st.icpsr.irq_d;
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		m_st.cpsr.b.fiq_d      = m_st.icpsr.fiq_d;
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		m_st.cpsr.b.thumb      = m_st.icpsr.thumb;
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		m_st.cpsr.b.s_overflow = m_st.icpsr.s_overflow;
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		m_st.cpsr.b.f_overflow = m_st.icpsr.f_overflow;
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		m_st.cpsr.b.f_carry    = m_st.icpsr.f_carry;
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		m_st.cpsr.b.f_zero     = m_st.icpsr.f_zero;
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		m_st.cpsr.b.f_sign     = m_st.icpsr.f_sign;
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	}
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	void Cpu::SwitchToMode (uint8_t newmode)
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	{
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		SaveMode(m_st.icpsr.mode);
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84
		switch (newmode)
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		{
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			case 0x10: // User (non-privileged)
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			case 0x1F: // System (privileged 'User' mode)
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				switch (m_st.icpsr.mode)
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				{
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					case 0x10:
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					case 0x1F:
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					case 0x11:
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						std::memcpy(m_st.r + 8, m_st.usr_r, sizeof(m_st.usr_r));
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						break;
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					default:
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						std::memcpy(m_st.r + 13, m_st.usr_r + 5, 2*4);
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						break;
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				}
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				break;
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			case 0x11: // FIQ
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				std::memcpy(m_st.r + 8, m_st.fiq_r, sizeof(m_st.fiq_r));
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				break;
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			case 0x12: // IRQ
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				std::memcpy(m_st.r + 13, m_st.irq_r, sizeof(m_st.irq_r));
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				break;
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			case 0x13: // Supervisor (SWI)
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				std::memcpy(m_st.r + 13, m_st.svc_r, sizeof(m_st.svc_r));
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				break;
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			case 0x17: // Abort
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				std::memcpy(m_st.r + 13, m_st.abt_r, sizeof(m_st.abt_r));
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				break;
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			case 0x1B: // Undefined
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				std::memcpy(m_st.r + 13, m_st.und_r, sizeof(m_st.und_r));
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				break;
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			default:
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				met_abort("Unknown CPU mode : " << IOS_ADD << (int)newmode);
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				break;
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		}
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		UpdateCpsr();
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		m_st.spsr.dw = m_st.cpsr.dw;
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		m_st.icpsr.mode = newmode;
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	}
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	void Cpu::SwitchModeBack ()
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	{
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		// oldmode is the mode on which we want to switch back
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		uint8_t oldmode = m_st.spsr.b.mode, curmode = m_st.icpsr.mode;
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		// we don't care if the spsr of the mode we are using is modified
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		SaveMode(curmode);
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132
		m_st.cpsr.dw = m_st.spsr.dw;
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		UpdateICpsr();
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		CheckInterrupt();
135
		switch (oldmode)
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		{
137
			case 0x10: // User (non-privileged)
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			case 0x1F: // System (privileged 'User' mode)
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				switch (curmode)
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				{
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					case 0x10:
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					case 0x1F:
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					case 0x11:
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						std::memcpy(m_st.r + 8, m_st.usr_r, sizeof(m_st.usr_r));
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						break;
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					default:
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						std::memcpy(m_st.r + 13, m_st.usr_r + 5, 2*4);
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						break;
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				}
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				break;
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			case 0x11: // FIQ
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				std::memcpy(m_st.r + 8, m_st.fiq_r, sizeof(m_st.fiq_r));
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				m_st.spsr.dw = m_st.fiq_spsr.dw;
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				break;
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			case 0x12: // IRQ
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				std::memcpy(m_st.r + 13, m_st.irq_r, sizeof(m_st.irq_r));
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				m_st.spsr.dw = m_st.irq_spsr.dw;
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				break;
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			case 0x13: // Supervisor (SWI)
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				std::memcpy(m_st.r + 13, m_st.svc_r, sizeof(m_st.svc_r));
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				m_st.spsr.dw = m_st.svc_spsr.dw;
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				break;
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			case 0x17: // Abort
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				std::memcpy(m_st.r + 13, m_st.abt_r, sizeof(m_st.abt_r));
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				m_st.spsr.dw = m_st.abt_spsr.dw;
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				break;
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			case 0x1B: // Undefined
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				std::memcpy(m_st.r + 13, m_st.und_r, sizeof(m_st.und_r));
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				m_st.spsr.dw = m_st.und_spsr.dw;
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				break;
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			default:
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				met_abort("Unknown CPU mode : " << IOS_ADD << (int)oldmode);
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				break;
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		}
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	}
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	void Cpu::SaveMode (uint8_t mode)
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	{
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		switch (mode)
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		{
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			case 0x10: // User (non-privileged)
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			case 0x1F: // System (privileged 'User' mode)
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				std::memcpy(m_st.usr_r, m_st.r + 8, sizeof(m_st.usr_r));
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				break;
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			case 0x11: // FIQ
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				std::memcpy(m_st.fiq_r, m_st.r + 8, sizeof(m_st.fiq_r));
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				m_st.fiq_spsr.dw = m_st.spsr.dw;
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				break;
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			case 0x12: // IRQ
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				std::memcpy(m_st.irq_r, m_st.r + 13, sizeof(m_st.irq_r));
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				m_st.irq_spsr.dw = m_st.spsr.dw;
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				break;
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			case 0x13: // Supervisor (SWI)
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				std::memcpy(m_st.svc_r, m_st.r + 13, sizeof(m_st.svc_r));
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				m_st.svc_spsr.dw = m_st.spsr.dw;
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				break;
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			case 0x17: // Abort
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				std::memcpy(m_st.abt_r, m_st.r + 13, sizeof(m_st.abt_r));
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				m_st.abt_spsr.dw = m_st.spsr.dw;
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				break;
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			case 0x1B: // Undefined
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				std::memcpy(m_st.und_r, m_st.r + 13, sizeof(m_st.und_r));
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				m_st.und_spsr.dw = m_st.spsr.dw;
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				break;
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			default:
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				met_abort("Unknown CPU mode : " << IOS_ADD << (int)mode);
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				break;
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		}
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	}
210

211
	void Cpu::Interrupt ()
212
	{
213
		// Switch mode
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		SwitchToMode(0x12); // IRQ
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		// Save PC
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		R(14) = R(15);
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		// FIXME : why ? this seems to be USELESS ! (look at bios irq end)
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		if (m_st.icpsr.thumb)
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			R(14) += 2;
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		// Switch to ARM
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		m_st.icpsr.thumb = false;
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		// Disable IRQ
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		m_st.icpsr.irq_d = true;
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		SetInterrupt(false);
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		// Branch on 0x18
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		R(15) = 0x1C;
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	}
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229
	void Cpu::SoftwareInterrupt ()
230
	{
231
		// Switch mode
232
		SwitchToMode(0x13); // Supervisor
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		// Save PC
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		R(14) = R(15) - (m_st.icpsr.thumb ? 2 : 4);
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		// Switch to ARM
236
		m_st.icpsr.thumb = false;
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		// Disable IRQ
238
		m_st.icpsr.irq_d = true;
239
		SetInterrupt(false);
240
		// Branch on 0x8
241
		R(15) = 0xC;
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	}
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244
	// TODO put this in Bios, no ?
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	void Cpu::SoftwareInterrupt (uint32_t comment)
246
	{
247
		if (true)
248
		{
249
			char buff[256];
250
			int pos = 0;
251
			pos += sprintf (buff + pos, "SWI %02xh : ", comment);
252
			switch (comment) // no one cares about the sound driver
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			{
254
			case 0x00: pos += sprintf (buff + pos, "SoftReset");
255
				break;
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			case 0x01: pos += sprintf (buff + pos, "RegisterRamReset"); // todo: display flags
257
				break;
258
			case 0x02: pos += sprintf (buff + pos, "Halt");
259
				break;
260
			case 0x03: pos += sprintf (buff + pos, "Stop");
261
				break;
262
			case 0x04: pos += sprintf (buff + pos, "IntrWait"); // todo: display flags
263
				break;
264
			case 0x05: pos += sprintf (buff + pos, "VBlankIntrWait");
265
				break;
266
			case 0x06: pos += sprintf (buff + pos, "Div: ");
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				pos += sprintf (buff + pos, "%08xh/%08xh", R(0), R(1));
268
				break;
269
			case 0x07: pos += sprintf (buff + pos, "DivArm: ");
270
				pos += sprintf (buff + pos, "%08xh/%08xh", R(1), R(0));
271
				break;
272
			case 0x08: pos += sprintf (buff + pos, "Sqrt: ");
273
				pos += sprintf (buff + pos, "sqrt(%08xh)", R(0));
274
				break;
275
			case 0x09: pos += sprintf (buff + pos, "ArcTan: ");
276
				pos += sprintf (buff + pos, "atan(%04xh)", R(0) & 0xffff);
277
				break;
278
			case 0x0a: pos += sprintf (buff + pos, "ArcTan2: ");
279
				pos += sprintf (buff + pos, "atan2(%04xh,%04xh)", R(1) & 0xffff, R(0) & 0xffff);
280
				break;
281
			case 0x0b: pos += sprintf (buff + pos, "CpuSet: ");
282
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh], wcnt=%xh, fixed=%c, size=%d", R(0), R(1), R(2) & 0x1fffff, R(2) & 0x1000000 ? 'Y' : 'N', R(2) & 0x4000000 ? 32 : 16);
283
				break;
284
			case 0x0c: pos += sprintf (buff + pos, "CpuFastSet: ");
285
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh], wcnt=%xh, fixed=%c", R(0), R(1), R(2) & 0x1fffff, R(2) & 0x1000000 ? 'Y' : 'N');
286
				break;
287
			case 0x0d: pos += sprintf (buff + pos, "GetBiosChecksum");
288
				break;
289
			case 0x0e: pos += sprintf (buff + pos, "BgAffineSet: ");
290
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh], cnt=%d", R(0), R(1), R(2));
291
				break;
292
			case 0x0f: pos += sprintf (buff + pos, "ObjAffineSet: ");
293
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh], cnt=%d, offs=%d", R(0), R(1), R(2), R(3));
294
				break;
295
			case 0x10: pos += sprintf (buff + pos, "BitUnPack: ");
296
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh], info=[%08xh]", R(0), R(1), R(2));
297
				break;
298
			case 0x11: pos += sprintf (buff + pos, "LZ77UnCompWram: ");
299
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
300
				break;
301
			case 0x12: pos += sprintf (buff + pos, "LZ77UnCompVram: ");
302
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
303
				break;
304
			case 0x13: pos += sprintf (buff + pos, "HuffUnComp: ");
305
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
306
				break;
307
			case 0x14: pos += sprintf (buff + pos, "RLUnCompWram: ");
308
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
309
				break;
310
			case 0x15: pos += sprintf (buff + pos, "RLUnCompVram: ");
311
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
312
				break;
313
			case 0x16: pos += sprintf (buff + pos, "Diff8bitUnFilterWram: ");
314
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
315
				break;
316
			case 0x17: pos += sprintf (buff + pos, "Diff8bitUnFilterVram: ");
317
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
318
				break;
319
			case 0x18: pos += sprintf (buff + pos, "Diff16bitUnFilter: ");
320
				pos += sprintf (buff + pos, "src=[%08xh], dst=[%08xh]", R(0), R(1));
321
				break;
322
			case 0x19: pos += sprintf (buff + pos, "SoundBias");
323
				break;
324
			case 0x1a: pos += sprintf (buff + pos, "SoundDriverInit");
325
				break;
326
			case 0x1b: pos += sprintf (buff + pos, "SoundDriverMode");
327
				break;
328
			case 0x1c: pos += sprintf (buff + pos, "SoundDriverMain");
329
				break;
330
			case 0x1d: pos += sprintf (buff + pos, "SoundDriverVSync");
331
				break;
332
			case 0x1e: pos += sprintf (buff + pos, "SoundChannelClear");
333
				break;
334
			case 0x1f: pos += sprintf (buff + pos, "MidiKey2Freq");
335
				break;
336
			case 0x20: pos += sprintf (buff + pos, "SoundWhatever0");
337
				break;
338
			case 0x21: pos += sprintf (buff + pos, "SoundWhatever1");
339
				break;
340
			case 0x22: pos += sprintf (buff + pos, "SoundWhatever2");
341
				break;
342
			case 0x23: pos += sprintf (buff + pos, "SoundWhatever3");
343
				break;
344
			case 0x24: pos += sprintf (buff + pos, "SoundWhatever4");
345
				break;
346
			case 0x25: pos += sprintf (buff + pos, "MultiBoot: ");
347
				pos += sprintf (buff + pos, "mbp=[%08xh], mode=%d", R(0), R(1));
348
				break;
349
			case 0x26: pos += sprintf (buff + pos, "HardReset");
350
				break;
351
			case 0x27: pos += sprintf (buff + pos, "CustomHalt: ");
352
				pos += sprintf (buff + pos, "val=%02xh", R(2) & 0xff);
353
				break;
354
			case 0x28: pos += sprintf (buff + pos, "SoundDriverVSyncOff");
355
				break;
356
			case 0x29: pos += sprintf (buff + pos, "SoundDriverVSyncOnn");
357
				break;
358
			case 0x2a: pos += sprintf (buff + pos, "SoundGetJumpList");
359
				break;
360
			default: pos += sprintf (buff + pos, "UNKNOWN");
361
				break;
362
			}
363
			pos += sprintf (buff + pos, "\n");
364
			print_bizhawk(buff);
365
		}
366
		if (MEM.HasBios())
367
			SoftwareInterrupt();
368
		else
369
			switch (comment)
370
			{
371
				case 0x00:
372
					Bios::SoftReset();
373
					break;
374
				case 0x01:
375
					Bios::RegisterRamReset();
376
					break;
377
				case 0x02:
378
					Bios::Halt();
379
					break;
380
				case 0x04:
381
				case 0x05:
382
					SoftwareInterrupt();
383
					break;
384
				case 0x06:
385
					Bios::Div();
386
					break;
387
				case 0x07:
388
					Bios::DivArm();
389
					break;
390
				case 0x08:
391
					Bios::Sqrt();
392
					break;
393
				case 0x09:
394
					Bios::ArcTan();
395
					break;
396
				case 0x0A:
397
					Bios::ArcTan2();
398
					break;
399
				case 0x0B:
400
					Bios::CpuSet();
401
					break;
402
				case 0x0C:
403
					Bios::CpuFastSet();
404
					break;
405
				case 0x0E:
406
					Bios::BgAffineSet();
407
					break;
408
				case 0x0F:
409
					Bios::ObjAffineSet();
410
					break;
411
				case 0x11:
412
					Bios::LZ77UnCompWram();
413
					break;
414
				case 0x12:
415
					Bios::LZ77UnCompVram();
416
					break;
417
				case 0x13:
418
					Bios::HuffUnComp();
419
					break;
420
				case 0x14:
421
					Bios::RLUnCompWram();
422
					break;
423
				case 0x15:
424
					Bios::RLUnCompVram();
425
					break;
426
				default:
427
					met_abort("Unknown software interrupt : " << IOS_ADD << comment);
428
					break;
429
			}
430
	}
431

432
	bool Cpu::SaveState (std::ostream& stream)
433
	{
434
		SS_WRITE_VAR(m_st);
435

436
		return true;
437
	}
438

439
	bool Cpu::LoadState (std::istream& stream)
440
	{
441
		SS_READ_VAR(m_st);
442

443
		CheckInterrupt();
444

445
		return true;
446
	}
447
}
448

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