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alexbevi
GitHub Repository: alexbevi/BizHawk
 Path: blob/master/libsnes/bsnes/snes/alt/smp/memory.cpp
2 views
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unsigned SMP::port_read(unsigned addr) {

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  return apuram[0xf4 + (addr & 3)];

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}

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void SMP::port_write(unsigned addr, unsigned data) {

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  apuram[0xf4 + (addr & 3)] = data;

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}

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unsigned SMP::mmio_read(unsigned addr) {

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  switch(addr) {

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  case 0xf2:

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    return status.dsp_addr;

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  case 0xf3:

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    return dsp.read(status.dsp_addr & 0x7f);

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  case 0xf4:

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  case 0xf5:

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  case 0xf6:

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  case 0xf7:

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    synchronize_cpu();

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    return cpu.port_read(addr);

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  case 0xf8:

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    return status.ram00f8;

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  case 0xf9:

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    return status.ram00f9;

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  case 0xfd: {

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    unsigned result = timer0.stage3_ticks & 15;

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    timer0.stage3_ticks = 0;

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    return result;

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  }

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  case 0xfe: {

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    unsigned result = timer1.stage3_ticks & 15;

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    timer1.stage3_ticks = 0;

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    return result;

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  }

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  case 0xff: {

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    unsigned result = timer2.stage3_ticks & 15;

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    timer2.stage3_ticks = 0;

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    return result;

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  }

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  }

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  return 0x00;

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}

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void SMP::mmio_write(unsigned addr, unsigned data) {

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  switch(addr) {

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  case 0xf1:

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    status.iplrom_enable = data & 0x80;

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    if(data & 0x30) {

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      synchronize_cpu();

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      if(data & 0x20) {

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        cpu.port_write(3, 0x00);

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        cpu.port_write(2, 0x00);

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      }

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      if(data & 0x10) {

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        cpu.port_write(1, 0x00);

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        cpu.port_write(0, 0x00);

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      }

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    }

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    if(timer2.enable == false && (data & 0x04)) {

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      timer2.stage2_ticks = 0;

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      timer2.stage3_ticks = 0;

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    }

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    timer2.enable = data & 0x04;

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    if(timer1.enable == false && (data & 0x02)) {

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      timer1.stage2_ticks = 0;

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      timer1.stage3_ticks = 0;

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    }

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    timer1.enable = data & 0x02;

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    if(timer0.enable == false && (data & 0x01)) {

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      timer0.stage2_ticks = 0;

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      timer0.stage3_ticks = 0;

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    }

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    timer0.enable = data & 0x01;

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    break;

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  case 0xf2:

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    status.dsp_addr = data;

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    break;

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  case 0xf3:

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    if(status.dsp_addr & 0x80) break;

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    dsp.write(status.dsp_addr, data);

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    break;

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  case 0xf4:

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  case 0xf5:

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  case 0xf6:

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  case 0xf7:

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    synchronize_cpu();

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    port_write(addr, data);

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    break;

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  case 0xf8:

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    status.ram00f8 = data;

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    break;

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  case 0xf9:

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    status.ram00f9 = data;

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    break;

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  case 0xfa:

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    timer0.target = data;

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    break;

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  case 0xfb:

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    timer1.target = data;

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    break;

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  case 0xfc:

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    timer2.target = data;

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    break;

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  }

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}

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