Path: blob/a-new-beginning/libavutil.xcframework/ios-arm64-simulator/libavutil.framework/Headers/cpu.h
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/*1* Copyright (c) 2000, 2001, 2002 Fabrice Bellard2*3* This file is part of FFmpeg.4*5* FFmpeg is free software; you can redistribute it and/or6* modify it under the terms of the GNU Lesser General Public7* License as published by the Free Software Foundation; either8* version 2.1 of the License, or (at your option) any later version.9*10* FFmpeg is distributed in the hope that it will be useful,11* but WITHOUT ANY WARRANTY; without even the implied warranty of12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU13* Lesser General Public License for more details.14*15* You should have received a copy of the GNU Lesser General Public16* License along with FFmpeg; if not, write to the Free Software17* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA18*/1920#ifndef AVUTIL_CPU_H21#define AVUTIL_CPU_H2223#include <stddef.h>2425#define AV_CPU_FLAG_FORCE 0x80000000 /* force usage of selected flags (OR) */2627/* lower 16 bits - CPU features */28#define AV_CPU_FLAG_MMX 0x0001 ///< standard MMX29#define AV_CPU_FLAG_MMXEXT 0x0002 ///< SSE integer functions or AMD MMX ext30#define AV_CPU_FLAG_MMX2 0x0002 ///< SSE integer functions or AMD MMX ext31#define AV_CPU_FLAG_3DNOW 0x0004 ///< AMD 3DNOW32#define AV_CPU_FLAG_SSE 0x0008 ///< SSE functions33#define AV_CPU_FLAG_SSE2 0x0010 ///< PIV SSE2 functions34#define AV_CPU_FLAG_SSE2SLOW 0x40000000 ///< SSE2 supported, but usually not faster35///< than regular MMX/SSE (e.g. Core1)36#define AV_CPU_FLAG_3DNOWEXT 0x0020 ///< AMD 3DNowExt37#define AV_CPU_FLAG_SSE3 0x0040 ///< Prescott SSE3 functions38#define AV_CPU_FLAG_SSE3SLOW 0x20000000 ///< SSE3 supported, but usually not faster39///< than regular MMX/SSE (e.g. Core1)40#define AV_CPU_FLAG_SSSE3 0x0080 ///< Conroe SSSE3 functions41#define AV_CPU_FLAG_SSSE3SLOW 0x4000000 ///< SSSE3 supported, but usually not faster42#define AV_CPU_FLAG_ATOM 0x10000000 ///< Atom processor, some SSSE3 instructions are slower43#define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions44#define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions45#define AV_CPU_FLAG_AESNI 0x80000 ///< Advanced Encryption Standard functions46#define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used47#define AV_CPU_FLAG_AVXSLOW 0x8000000 ///< AVX supported, but slow when using YMM registers (e.g. Bulldozer)48#define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions49#define AV_CPU_FLAG_FMA4 0x0800 ///< Bulldozer FMA4 functions50#define AV_CPU_FLAG_CMOV 0x1000 ///< supports cmov instruction51#define AV_CPU_FLAG_AVX2 0x8000 ///< AVX2 functions: requires OS support even if YMM registers aren't used52#define AV_CPU_FLAG_FMA3 0x10000 ///< Haswell FMA3 functions53#define AV_CPU_FLAG_BMI1 0x20000 ///< Bit Manipulation Instruction Set 154#define AV_CPU_FLAG_BMI2 0x40000 ///< Bit Manipulation Instruction Set 255#define AV_CPU_FLAG_AVX512 0x100000 ///< AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used56#define AV_CPU_FLAG_AVX512ICL 0x200000 ///< F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ57#define AV_CPU_FLAG_SLOW_GATHER 0x2000000 ///< CPU has slow gathers.5859#define AV_CPU_FLAG_ALTIVEC 0x0001 ///< standard60#define AV_CPU_FLAG_VSX 0x0002 ///< ISA 2.0661#define AV_CPU_FLAG_POWER8 0x0004 ///< ISA 2.076263#define AV_CPU_FLAG_ARMV5TE (1 << 0)64#define AV_CPU_FLAG_ARMV6 (1 << 1)65#define AV_CPU_FLAG_ARMV6T2 (1 << 2)66#define AV_CPU_FLAG_VFP (1 << 3)67#define AV_CPU_FLAG_VFPV3 (1 << 4)68#define AV_CPU_FLAG_NEON (1 << 5)69#define AV_CPU_FLAG_ARMV8 (1 << 6)70#define AV_CPU_FLAG_VFP_VM (1 << 7) ///< VFPv2 vector mode, deprecated in ARMv7-A and unavailable in various CPUs implementations71#define AV_CPU_FLAG_SETEND (1 <<16)7273#define AV_CPU_FLAG_MMI (1 << 0)74#define AV_CPU_FLAG_MSA (1 << 1)7576//Loongarch SIMD extension.77#define AV_CPU_FLAG_LSX (1 << 0)78#define AV_CPU_FLAG_LASX (1 << 1)7980// RISC-V extensions81#define AV_CPU_FLAG_RVI (1 << 0) ///< I (full GPR bank)82#define AV_CPU_FLAG_RVF (1 << 1) ///< F (single precision FP)83#define AV_CPU_FLAG_RVD (1 << 2) ///< D (double precision FP)84#define AV_CPU_FLAG_RVV_I32 (1 << 3) ///< Vectors of 8/16/32-bit int's */85#define AV_CPU_FLAG_RVV_F32 (1 << 4) ///< Vectors of float's */86#define AV_CPU_FLAG_RVV_I64 (1 << 5) ///< Vectors of 64-bit int's */87#define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's88#define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations8990/**91* Return the flags which specify extensions supported by the CPU.92* The returned value is affected by av_force_cpu_flags() if that was used93* before. So av_get_cpu_flags() can easily be used in an application to94* detect the enabled cpu flags.95*/96int av_get_cpu_flags(void);9798/**99* Disables cpu detection and forces the specified flags.100* -1 is a special case that disables forcing of specific flags.101*/102void av_force_cpu_flags(int flags);103104/**105* Parse CPU caps from a string and update the given AV_CPU_* flags based on that.106*107* @return negative on error.108*/109int av_parse_cpu_caps(unsigned *flags, const char *s);110111/**112* @return the number of logical CPU cores present.113*/114int av_cpu_count(void);115116/**117* Overrides cpu count detection and forces the specified count.118* Count < 1 disables forcing of specific count.119*/120void av_cpu_force_count(int count);121122/**123* Get the maximum data alignment that may be required by FFmpeg.124*125* Note that this is affected by the build configuration and the CPU flags mask,126* so e.g. if the CPU supports AVX, but libavutil has been built with127* --disable-avx or the AV_CPU_FLAG_AVX flag has been disabled through128* av_set_cpu_flags_mask(), then this function will behave as if AVX is not129* present.130*/131size_t av_cpu_max_align(void);132133#endif /* AVUTIL_CPU_H */134135136