CoCalc -- RegisterContextDarwin

GitHub Repository: freebsd/freebsd-src
Path: blob/main/contrib/llvm-project/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
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//===-- RegisterContextDarwin_riscv32.cpp
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//------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "lldb/Utility/DataBufferHeap.h"
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#include "lldb/Utility/DataExtractor.h"
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#include "lldb/Utility/Endian.h"
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#include "lldb/Utility/Log.h"
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#include "lldb/Utility/RegisterValue.h"
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#include "lldb/Utility/Scalar.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/Compiler.h"
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#include <cstddef>
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#include <memory>
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#include "RegisterContextDarwin_riscv32.h"
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#include "Utility/RISCV_DWARF_Registers.h"
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using namespace lldb;
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using namespace lldb_private;
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enum {
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  gpr_x0 = 0,
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  gpr_x1,
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  gpr_x2,
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  gpr_x3,
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  gpr_x4,
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  gpr_x5,
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  gpr_x6,
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  gpr_x7,
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  gpr_x8,
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  gpr_x9,
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  gpr_x10,
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  gpr_x11,
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  gpr_x12,
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  gpr_x13,
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  gpr_x14,
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  gpr_x15,
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  gpr_x16,
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  gpr_x17,
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  gpr_x18,
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  gpr_x19,
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  gpr_x20,
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  gpr_x21,
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  gpr_x22,
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  gpr_x23,
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  gpr_x24,
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  gpr_x25,
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  gpr_x26,
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  gpr_x27,
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  gpr_x28,
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  gpr_x29,
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  gpr_x30,
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  gpr_x31,
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  gpr_pc,
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  fpr_f0,
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  fpr_f1,
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  fpr_f2,
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  fpr_f3,
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  fpr_f4,
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  fpr_f5,
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  fpr_f6,
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  fpr_f7,
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  fpr_f8,
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  fpr_f9,
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  fpr_f10,
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  fpr_f11,
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  fpr_f12,
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  fpr_f13,
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  fpr_f14,
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  fpr_f15,
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  fpr_f16,
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  fpr_f17,
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  fpr_f18,
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  fpr_f19,
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  fpr_f20,
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  fpr_f21,
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  fpr_f22,
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  fpr_f23,
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  fpr_f24,
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  fpr_f25,
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  fpr_f26,
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  fpr_f27,
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  fpr_f28,
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  fpr_f29,
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  fpr_f30,
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  fpr_f31,
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  fpr_fcsr,
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  exc_exception,
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  exc_fsr,
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  exc_far,
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  csr_bank,
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  k_num_registers
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};
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/* clang-format off */
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#define GPR_OFFSET(reg)                                                        \
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  (LLVM_EXTENSION offsetof(RegisterContextDarwin_riscv32::GPR, reg))
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#define FPU_OFFSET(reg)                                                        \
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  (LLVM_EXTENSION offsetof(RegisterContextDarwin_riscv32::FPU, reg) +          \
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   sizeof(RegisterContextDarwin_riscv32::GPR))
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#define EXC_OFFSET(reg)                                                        \
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  (LLVM_EXTENSION offsetof(RegisterContextDarwin_riscv32::EXC, reg) +          \
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   sizeof(RegisterContextDarwin_riscv32::GPR) +                                \
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   sizeof(RegisterContextDarwin_riscv32::FPU))
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// These macros will auto define the register name, alt name, register size,
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// register offset, encoding, format and native register. This ensures that the
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// register state structures are defined correctly and have the correct sizes
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// and offsets.
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#define DEFINE_GPR_ABI(reg, canon)                                             \
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      #reg, #canon,                                                            \
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      sizeof(((RegisterContextDarwin_riscv32::GPR *)nullptr)->canon),          \
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      GPR_OFFSET(canon), eEncodingUint, eFormatHex
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#define DEFINE_GPR(reg)                                                        \
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      #reg, nullptr,                                                           \
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      sizeof(((RegisterContextDarwin_riscv32::GPR *)nullptr)->reg),            \
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      GPR_OFFSET(reg), eEncodingUint, eFormatHex
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#define DEFINE_FPU_ABI(reg, canon)                                             \
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      #reg, #canon,                                                            \
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      sizeof(((RegisterContextDarwin_riscv32::FPU *)nullptr)->canon),          \
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      FPU_OFFSET(canon), eEncodingUint, eFormatHex
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#define DEFINE_FPU(reg)                                                        \
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      #reg, nullptr,                                                           \
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      sizeof(((RegisterContextDarwin_riscv32::FPU *)nullptr)->reg),            \
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      FPU_OFFSET(reg), eEncodingUint, eFormatHex
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#define DEFINE_EXC(reg)                                                        \
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      #reg, nullptr,                                                           \
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      sizeof(((RegisterContextDarwin_riscv32::EXC *)nullptr)->reg),            \
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      EXC_OFFSET(reg), eEncodingUint, eFormatHex
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#define REG_CONTEXT_SIZE                                                       \
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  (sizeof(RegisterContextDarwin_riscv32::GPR) +                                \
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   sizeof(RegisterContextDarwin_riscv32::FPU) +                                \
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   sizeof(RegisterContextDarwin_riscv32::EXC) +                                \
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   sizeof(RegisterContextDarwin_riscv32::CSR))
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/* clang-format on */
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static RegisterInfo g_register_infos[] = {
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    {
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        DEFINE_GPR_ABI(zero, x0),
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        {riscv_dwarf::dwarf_gpr_x0, riscv_dwarf::dwarf_gpr_x0,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x0},
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        nullptr,
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        nullptr,
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        nullptr,
157
    },
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    {
159
        DEFINE_GPR_ABI(ra, x1),
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        {riscv_dwarf::dwarf_gpr_x1, riscv_dwarf::dwarf_gpr_x1,
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         LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, gpr_x1},
162
        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(sp, x2),
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        {riscv_dwarf::dwarf_gpr_x2, riscv_dwarf::dwarf_gpr_x2,
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         LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, gpr_x2},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(gp, x3),
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        {riscv_dwarf::dwarf_gpr_x3, riscv_dwarf::dwarf_gpr_x3,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x3},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(tp, x4),
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        {riscv_dwarf::dwarf_gpr_x4, riscv_dwarf::dwarf_gpr_x4,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x4},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(t0, x5),
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        {riscv_dwarf::dwarf_gpr_x5, riscv_dwarf::dwarf_gpr_x5,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x5},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(t1, x6),
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        {riscv_dwarf::dwarf_gpr_x6, riscv_dwarf::dwarf_gpr_x6,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x6},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(t2, x7),
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        {riscv_dwarf::dwarf_gpr_x7, riscv_dwarf::dwarf_gpr_x7,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x7},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(fp, x8),
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        {riscv_dwarf::dwarf_gpr_x8, riscv_dwarf::dwarf_gpr_x8,
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         LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, gpr_x8},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(s1, x9),
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        {riscv_dwarf::dwarf_gpr_x9, riscv_dwarf::dwarf_gpr_x9,
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         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x9},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(a0, x10),
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        {riscv_dwarf::dwarf_gpr_x10, riscv_dwarf::dwarf_gpr_x10,
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         LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, gpr_x10},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(a1, x11),
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        {riscv_dwarf::dwarf_gpr_x11, riscv_dwarf::dwarf_gpr_x11,
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         LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, gpr_x11},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(a2, x12),
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        {riscv_dwarf::dwarf_gpr_x12, riscv_dwarf::dwarf_gpr_x12,
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         LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, gpr_x12},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(a3, x13),
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        {riscv_dwarf::dwarf_gpr_x13, riscv_dwarf::dwarf_gpr_x13,
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         LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, gpr_x13},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(a4, x14),
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        {riscv_dwarf::dwarf_gpr_x14, riscv_dwarf::dwarf_gpr_x14,
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         LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM, gpr_x14},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
271
        DEFINE_GPR_ABI(a5, x15),
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        {riscv_dwarf::dwarf_gpr_x15, riscv_dwarf::dwarf_gpr_x15,
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         LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM, gpr_x15},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
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        DEFINE_GPR_ABI(a6, x16),
280
        {riscv_dwarf::dwarf_gpr_x16, riscv_dwarf::dwarf_gpr_x16,
281
         LLDB_REGNUM_GENERIC_ARG7, LLDB_INVALID_REGNUM, gpr_x16},
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        nullptr,
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        nullptr,
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        nullptr,
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    },
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    {
287
        DEFINE_GPR_ABI(a7, x17),
288
        {riscv_dwarf::dwarf_gpr_x17, riscv_dwarf::dwarf_gpr_x17,
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         LLDB_REGNUM_GENERIC_ARG8, LLDB_INVALID_REGNUM, gpr_x17},
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        nullptr,
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        nullptr,
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        nullptr,
293
    },
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    {
295
        DEFINE_GPR_ABI(s2, x18),
296
        {riscv_dwarf::dwarf_gpr_x18, riscv_dwarf::dwarf_gpr_x18,
297
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x18},
298
        nullptr,
299
        nullptr,
300
        nullptr,
301
    },
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    {
303
        DEFINE_GPR_ABI(s3, x19),
304
        {riscv_dwarf::dwarf_gpr_x19, riscv_dwarf::dwarf_gpr_x19,
305
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x19},
306
        nullptr,
307
        nullptr,
308
        nullptr,
309
    },
310
    {
311
        DEFINE_GPR_ABI(s4, x20),
312
        {riscv_dwarf::dwarf_gpr_x20, riscv_dwarf::dwarf_gpr_x20,
313
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x20},
314
        nullptr,
315
        nullptr,
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        nullptr,
317
    },
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    {
319
        DEFINE_GPR_ABI(s5, x21),
320
        {riscv_dwarf::dwarf_gpr_x21, riscv_dwarf::dwarf_gpr_x21,
321
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x21},
322
        nullptr,
323
        nullptr,
324
        nullptr,
325
    },
326
    {
327
        DEFINE_GPR_ABI(s6, x22),
328
        {riscv_dwarf::dwarf_gpr_x22, riscv_dwarf::dwarf_gpr_x22,
329
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x22},
330
        nullptr,
331
        nullptr,
332
        nullptr,
333
    },
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    {
335
        DEFINE_GPR_ABI(s7, x23),
336
        {riscv_dwarf::dwarf_gpr_x23, riscv_dwarf::dwarf_gpr_x23,
337
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x23},
338
        nullptr,
339
        nullptr,
340
        nullptr,
341
    },
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    {
343
        DEFINE_GPR_ABI(s8, x24),
344
        {riscv_dwarf::dwarf_gpr_x24, riscv_dwarf::dwarf_gpr_x24,
345
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x24},
346
        nullptr,
347
        nullptr,
348
        nullptr,
349
    },
350
    {
351
        DEFINE_GPR_ABI(s9, x25),
352
        {riscv_dwarf::dwarf_gpr_x25, riscv_dwarf::dwarf_gpr_x25,
353
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x25},
354
        nullptr,
355
        nullptr,
356
        nullptr,
357
    },
358
    {
359
        DEFINE_GPR_ABI(s10, x26),
360
        {riscv_dwarf::dwarf_gpr_x26, riscv_dwarf::dwarf_gpr_x26,
361
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x26},
362
        nullptr,
363
        nullptr,
364
        nullptr,
365
    },
366
    {
367
        DEFINE_GPR_ABI(s11, x27),
368
        {riscv_dwarf::dwarf_gpr_x27, riscv_dwarf::dwarf_gpr_x27,
369
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x27},
370
        nullptr,
371
        nullptr,
372
        nullptr,
373
    },
374
    {
375
        DEFINE_GPR_ABI(t3, x28),
376
        {riscv_dwarf::dwarf_gpr_x28, riscv_dwarf::dwarf_gpr_x28,
377
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x28},
378
        nullptr,
379
        nullptr,
380
        nullptr,
381
    },
382
    {
383
        DEFINE_GPR_ABI(t4, x29),
384
        {riscv_dwarf::dwarf_gpr_x29, riscv_dwarf::dwarf_gpr_x29,
385
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x29},
386
        nullptr,
387
        nullptr,
388
        nullptr,
389
    },
390
    {
391
        DEFINE_GPR_ABI(t5, x30),
392
        {riscv_dwarf::dwarf_gpr_x30, riscv_dwarf::dwarf_gpr_x30,
393
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x30},
394
        nullptr,
395
        nullptr,
396
        nullptr,
397
    },
398
    {
399
        DEFINE_GPR_ABI(t6, x31),
400
        {riscv_dwarf::dwarf_gpr_x31, riscv_dwarf::dwarf_gpr_x31,
401
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x31},
402
        nullptr,
403
        nullptr,
404
        nullptr,
405
    },
406
    {
407
        DEFINE_GPR(pc),
408
        {riscv_dwarf::dwarf_gpr_pc, riscv_dwarf::dwarf_gpr_pc,
409
         LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, gpr_pc},
410
        nullptr,
411
        nullptr,
412
        nullptr,
413
    },
414

415
    {
416
        DEFINE_FPU_ABI(ft0, f0),
417
        {riscv_dwarf::dwarf_fpr_f0, riscv_dwarf::dwarf_fpr_f0,
418
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f0},
419
        nullptr,
420
        nullptr,
421
        nullptr,
422
    },
423
    {
424
        DEFINE_FPU_ABI(ft1, f1),
425
        {riscv_dwarf::dwarf_fpr_f1, riscv_dwarf::dwarf_fpr_f1,
426
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f1},
427
        nullptr,
428
        nullptr,
429
        nullptr,
430
    },
431
    {
432
        DEFINE_FPU_ABI(ft2, f2),
433
        {riscv_dwarf::dwarf_fpr_f2, riscv_dwarf::dwarf_fpr_f2,
434
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f2},
435
        nullptr,
436
        nullptr,
437
        nullptr,
438
    },
439
    {
440
        DEFINE_FPU_ABI(ft3, f3),
441
        {riscv_dwarf::dwarf_fpr_f3, riscv_dwarf::dwarf_fpr_f3,
442
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f3},
443
        nullptr,
444
        nullptr,
445
        nullptr,
446
    },
447
    {
448
        DEFINE_FPU_ABI(ft4, f4),
449
        {riscv_dwarf::dwarf_fpr_f4, riscv_dwarf::dwarf_fpr_f4,
450
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f4},
451
        nullptr,
452
        nullptr,
453
        nullptr,
454
    },
455
    {
456
        DEFINE_FPU_ABI(ft5, f5),
457
        {riscv_dwarf::dwarf_fpr_f5, riscv_dwarf::dwarf_fpr_f5,
458
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f5},
459
        nullptr,
460
        nullptr,
461
        nullptr,
462
    },
463
    {
464
        DEFINE_FPU_ABI(ft6, f6),
465
        {riscv_dwarf::dwarf_fpr_f6, riscv_dwarf::dwarf_fpr_f6,
466
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f6},
467
        nullptr,
468
        nullptr,
469
        nullptr,
470
    },
471
    {
472
        DEFINE_FPU_ABI(ft7, f7),
473
        {riscv_dwarf::dwarf_fpr_f7, riscv_dwarf::dwarf_fpr_f7,
474
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f7},
475
        nullptr,
476
        nullptr,
477
        nullptr,
478
    },
479
    {
480
        DEFINE_FPU_ABI(fs0, f8),
481
        {riscv_dwarf::dwarf_fpr_f8, riscv_dwarf::dwarf_fpr_f8,
482
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f8},
483
        nullptr,
484
        nullptr,
485
        nullptr,
486
    },
487
    {
488
        DEFINE_FPU_ABI(fs1, f9),
489
        {riscv_dwarf::dwarf_fpr_f9, riscv_dwarf::dwarf_fpr_f9,
490
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f9},
491
        nullptr,
492
        nullptr,
493
        nullptr,
494
    },
495
    {
496
        DEFINE_FPU_ABI(fa0, f10),
497
        {riscv_dwarf::dwarf_fpr_f10, riscv_dwarf::dwarf_fpr_f10,
498
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f10},
499
        nullptr,
500
        nullptr,
501
        nullptr,
502
    },
503
    {
504
        DEFINE_FPU_ABI(fa1, f11),
505
        {riscv_dwarf::dwarf_fpr_f11, riscv_dwarf::dwarf_fpr_f11,
506
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f11},
507
        nullptr,
508
        nullptr,
509
        nullptr,
510
    },
511
    {
512
        DEFINE_FPU_ABI(fa2, f12),
513
        {riscv_dwarf::dwarf_fpr_f12, riscv_dwarf::dwarf_fpr_f12,
514
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f12},
515
        nullptr,
516
        nullptr,
517
        nullptr,
518
    },
519
    {
520
        DEFINE_FPU_ABI(fa3, f13),
521
        {riscv_dwarf::dwarf_fpr_f13, riscv_dwarf::dwarf_fpr_f13,
522
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f13},
523
        nullptr,
524
        nullptr,
525
        nullptr,
526
    },
527
    {
528
        DEFINE_FPU_ABI(fa4, f14),
529
        {riscv_dwarf::dwarf_fpr_f14, riscv_dwarf::dwarf_fpr_f14,
530
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f14},
531
        nullptr,
532
        nullptr,
533
        nullptr,
534
    },
535
    {
536
        DEFINE_FPU_ABI(fa5, f15),
537
        {riscv_dwarf::dwarf_fpr_f15, riscv_dwarf::dwarf_fpr_f15,
538
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f15},
539
        nullptr,
540
        nullptr,
541
        nullptr,
542
    },
543
    {
544
        DEFINE_FPU_ABI(fa6, f16),
545
        {riscv_dwarf::dwarf_fpr_f16, riscv_dwarf::dwarf_fpr_f16,
546
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f16},
547
        nullptr,
548
        nullptr,
549
        nullptr,
550
    },
551
    {
552
        DEFINE_FPU_ABI(fa7, f17),
553
        {riscv_dwarf::dwarf_fpr_f17, riscv_dwarf::dwarf_fpr_f17,
554
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f17},
555
        nullptr,
556
        nullptr,
557
        nullptr,
558
    },
559
    {
560
        DEFINE_FPU_ABI(fs2, f18),
561
        {riscv_dwarf::dwarf_fpr_f18, riscv_dwarf::dwarf_fpr_f18,
562
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f18},
563
        nullptr,
564
        nullptr,
565
        nullptr,
566
    },
567
    {
568
        DEFINE_FPU_ABI(fs3, f19),
569
        {riscv_dwarf::dwarf_fpr_f19, riscv_dwarf::dwarf_fpr_f19,
570
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f19},
571
        nullptr,
572
        nullptr,
573
        nullptr,
574
    },
575
    {
576
        DEFINE_FPU_ABI(fs4, f20),
577
        {riscv_dwarf::dwarf_fpr_f20, riscv_dwarf::dwarf_fpr_f20,
578
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f20},
579
        nullptr,
580
        nullptr,
581
        nullptr,
582
    },
583
    {
584
        DEFINE_FPU_ABI(fs5, f21),
585
        {riscv_dwarf::dwarf_fpr_f21, riscv_dwarf::dwarf_fpr_f21,
586
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f21},
587
        nullptr,
588
        nullptr,
589
        nullptr,
590
    },
591
    {
592
        DEFINE_FPU_ABI(fs6, f22),
593
        {riscv_dwarf::dwarf_fpr_f22, riscv_dwarf::dwarf_fpr_f22,
594
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f22},
595
        nullptr,
596
        nullptr,
597
        nullptr,
598
    },
599
    {
600
        DEFINE_FPU_ABI(fs7, f23),
601
        {riscv_dwarf::dwarf_fpr_f23, riscv_dwarf::dwarf_fpr_f23,
602
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f23},
603
        nullptr,
604
        nullptr,
605
        nullptr,
606
    },
607
    {
608
        DEFINE_FPU_ABI(fs8, f24),
609
        {riscv_dwarf::dwarf_fpr_f24, riscv_dwarf::dwarf_fpr_f24,
610
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f24},
611
        nullptr,
612
        nullptr,
613
        nullptr,
614
    },
615
    {
616
        DEFINE_FPU_ABI(fs9, f25),
617
        {riscv_dwarf::dwarf_fpr_f25, riscv_dwarf::dwarf_fpr_f25,
618
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f25},
619
        nullptr,
620
        nullptr,
621
        nullptr,
622
    },
623
    {
624
        DEFINE_FPU_ABI(fs10, f26),
625
        {riscv_dwarf::dwarf_fpr_f26, riscv_dwarf::dwarf_fpr_f26,
626
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f26},
627
        nullptr,
628
        nullptr,
629
        nullptr,
630
    },
631
    {
632
        DEFINE_FPU_ABI(fs11, f27),
633
        {riscv_dwarf::dwarf_fpr_f27, riscv_dwarf::dwarf_fpr_f27,
634
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f27},
635
        nullptr,
636
        nullptr,
637
        nullptr,
638
    },
639
    {
640
        DEFINE_FPU_ABI(ft8, f28),
641
        {riscv_dwarf::dwarf_fpr_f28, riscv_dwarf::dwarf_fpr_f28,
642
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f28},
643
        nullptr,
644
        nullptr,
645
        nullptr,
646
    },
647
    {
648
        DEFINE_FPU_ABI(ft9, f29),
649
        {riscv_dwarf::dwarf_fpr_f29, riscv_dwarf::dwarf_fpr_f29,
650
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f29},
651
        nullptr,
652
        nullptr,
653
        nullptr,
654
    },
655
    {
656
        DEFINE_FPU_ABI(ft10, f30),
657
        {riscv_dwarf::dwarf_fpr_f30, riscv_dwarf::dwarf_fpr_f30,
658
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f30},
659
        nullptr,
660
        nullptr,
661
        nullptr,
662
    },
663
    {
664
        DEFINE_FPU_ABI(ft11, f31),
665
        {riscv_dwarf::dwarf_fpr_f31, riscv_dwarf::dwarf_fpr_f31,
666
         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f31},
667
        nullptr,
668
        nullptr,
669
        nullptr,
670
    },
671
    {
672
        DEFINE_FPU(fcsr),
673
        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
674
         LLDB_INVALID_REGNUM, fpr_fcsr},
675
        nullptr,
676
        nullptr,
677
        nullptr,
678
    },
679

680
    {
681
        DEFINE_EXC(exception),
682
        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
683
         LLDB_INVALID_REGNUM, exc_exception},
684
        nullptr,
685
        nullptr,
686
        nullptr,
687
    },
688
    {
689
        DEFINE_EXC(fsr),
690
        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
691
         LLDB_INVALID_REGNUM, exc_fsr},
692
        nullptr,
693
        nullptr,
694
        nullptr,
695
    },
696
    {
697
        DEFINE_EXC(far),
698
        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
699
         LLDB_INVALID_REGNUM, exc_far},
700
        nullptr,
701
        nullptr,
702
        nullptr,
703
    },
704
    {"csr",
705
     nullptr,
706
     1024 * sizeof(uint32_t),
707
     0,
708
     eEncodingVector,
709
     eFormatVectorOfUInt32,
710
     {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
711
      LLDB_INVALID_REGNUM, csr_bank},
712
     nullptr,
713
     nullptr,
714
     nullptr}};
715

716
static size_t k_num_register_infos = std::size(g_register_infos);
717

718
RegisterContextDarwin_riscv32::RegisterContextDarwin_riscv32(
719
    Thread &thread, uint32_t concrete_frame_idx)
720
    : RegisterContext(thread, concrete_frame_idx), gpr(), fpr(), exc() {
721
  uint32_t i;
722
  for (i = 0; i < kNumErrors; i++) {
723
    gpr_errs[i] = -1;
724
    fpr_errs[i] = -1;
725
    exc_errs[i] = -1;
726
    csr_errs[i] = -1;
727
  }
728
}
729

730
RegisterContextDarwin_riscv32::~RegisterContextDarwin_riscv32() = default;
731

732
void RegisterContextDarwin_riscv32::InvalidateAllRegisters() {
733
  InvalidateAllRegisterStates();
734
}
735

736
size_t RegisterContextDarwin_riscv32::GetRegisterCount() {
737
  assert(k_num_register_infos == k_num_registers);
738
  return k_num_registers;
739
}
740

741
const RegisterInfo *
742
RegisterContextDarwin_riscv32::GetRegisterInfoAtIndex(size_t reg) {
743
  assert(k_num_register_infos == k_num_registers);
744
  if (reg < k_num_registers)
745
    return &g_register_infos[reg];
746
  return nullptr;
747
}
748

749
size_t RegisterContextDarwin_riscv32::GetRegisterInfosCount() {
750
  return k_num_register_infos;
751
}
752

753
const RegisterInfo *RegisterContextDarwin_riscv32::GetRegisterInfos() {
754
  return g_register_infos;
755
}
756

757
// General purpose registers
758
static uint32_t g_gpr_regnums[] = {
759
    gpr_x0,  gpr_x1,  gpr_x2,  gpr_x3,  gpr_x4,  gpr_x5,  gpr_x6,
760
    gpr_x7,  gpr_x8,  gpr_x9,  gpr_x10, gpr_x11, gpr_x12, gpr_x13,
761
    gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20,
762
    gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27,
763
    gpr_x28, gpr_x29, gpr_x30, gpr_x31, gpr_pc};
764

765
// Floating point registers
766
static uint32_t g_fpr_regnums[] = {
767
    fpr_f0,  fpr_f1,  fpr_f2,  fpr_f3,  fpr_f4,  fpr_f5,  fpr_f6,
768
    fpr_f7,  fpr_f8,  fpr_f9,  fpr_f10, fpr_f11, fpr_f12, fpr_f13,
769
    fpr_f14, fpr_f15, fpr_f16, fpr_f17, fpr_f18, fpr_f19, fpr_f20,
770
    fpr_f21, fpr_f22, fpr_f23, fpr_f24, fpr_f25, fpr_f26, fpr_f27,
771
    fpr_f28, fpr_f29, fpr_f30, fpr_f31, fpr_fcsr};
772

773
// Exception registers
774

775
static uint32_t g_exc_regnums[] = {exc_exception, exc_fsr, exc_far};
776

777
// CSR bank registers
778
static uint32_t g_csr_regnums[] = {csr_bank};
779

780
// Number of registers in each register set
781
const size_t k_num_gpr_registers = std::size(g_gpr_regnums);
782
const size_t k_num_fpr_registers = std::size(g_fpr_regnums);
783
const size_t k_num_exc_registers = std::size(g_exc_regnums);
784
const size_t k_num_csr_registers = std::size(g_csr_regnums);
785

786
// Register set definitions. The first definitions at register set index of
787
// zero is for all registers, followed by other registers sets. The register
788
// information for the all register set need not be filled in.
789
static const RegisterSet g_reg_sets[] = {
790
    {
791
        "General Purpose Registers",
792
        "gpr",
793
        k_num_gpr_registers,
794
        g_gpr_regnums,
795
    },
796
    {"Floating Point Registers", "fpr", k_num_fpr_registers, g_fpr_regnums},
797
    {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums},
798
    {"CSR register bank", "csr", k_num_csr_registers, g_csr_regnums}};
799

800
const size_t k_num_regsets = std::size(g_reg_sets);
801

802
size_t RegisterContextDarwin_riscv32::GetRegisterSetCount() {
803
  return k_num_regsets;
804
}
805

806
const RegisterSet *
807
RegisterContextDarwin_riscv32::GetRegisterSet(size_t reg_set) {
808
  if (reg_set < k_num_regsets)
809
    return &g_reg_sets[reg_set];
810
  return nullptr;
811
}
812

813
// Register information definitions for 32 bit riscv32.
814
int RegisterContextDarwin_riscv32::GetSetForNativeRegNum(int reg_num) {
815
  if (reg_num < fpr_f0)
816
    return GPRRegSet;
817
  else if (reg_num < exc_exception)
818
    return FPURegSet;
819
  else if (reg_num < csr_bank)
820
    return EXCRegSet;
821
  else if (reg_num < k_num_registers)
822
    return CSRRegSet;
823
  return -1;
824
}
825

826
void RegisterContextDarwin_riscv32::LogGPR(Log *log, const char *title) {
827
  if (log) {
828
    if (title)
829
      LLDB_LOGF(log, "%s", title);
830
    for (uint32_t i = 0; i < k_num_gpr_registers; i++) {
831
      uint32_t reg = gpr_x0 + i;
832
      LLDB_LOGF(log, "%12s = 0x%4.4x", g_register_infos[reg].name,
833
                (&gpr.x0)[reg]);
834
    }
835
  }
836
}
837

838
int RegisterContextDarwin_riscv32::ReadGPR(bool force) {
839
  int set = GPRRegSet;
840
  if (force || !RegisterSetIsCached(set)) {
841
    SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
842
  }
843
  return GetError(set, Read);
844
}
845

846
int RegisterContextDarwin_riscv32::ReadFPU(bool force) {
847
  int set = FPURegSet;
848
  if (force || !RegisterSetIsCached(set)) {
849
    SetError(set, Read, DoReadFPU(GetThreadID(), set, fpr));
850
  }
851
  return GetError(set, Read);
852
}
853

854
int RegisterContextDarwin_riscv32::ReadEXC(bool force) {
855
  int set = EXCRegSet;
856
  if (force || !RegisterSetIsCached(set)) {
857
    SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
858
  }
859
  return GetError(set, Read);
860
}
861

862
int RegisterContextDarwin_riscv32::ReadCSR(bool force) {
863
  int set = CSRRegSet;
864
  if (force || !RegisterSetIsCached(set)) {
865
    SetError(set, Read, DoReadCSR(GetThreadID(), set, csr));
866
  }
867
  return GetError(set, Read);
868
}
869

870
int RegisterContextDarwin_riscv32::WriteGPR() {
871
  int set = GPRRegSet;
872
  if (!RegisterSetIsCached(set)) {
873
    SetError(set, Write, -1);
874
    return -1;
875
  }
876
  SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
877
  SetError(set, Read, -1);
878
  return GetError(set, Write);
879
}
880

881
int RegisterContextDarwin_riscv32::WriteFPU() {
882
  int set = FPURegSet;
883
  if (!RegisterSetIsCached(set)) {
884
    SetError(set, Write, -1);
885
    return -1;
886
  }
887
  SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpr));
888
  SetError(set, Read, -1);
889
  return GetError(set, Write);
890
}
891

892
int RegisterContextDarwin_riscv32::WriteEXC() {
893
  int set = EXCRegSet;
894
  if (!RegisterSetIsCached(set)) {
895
    SetError(set, Write, -1);
896
    return -1;
897
  }
898
  SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
899
  SetError(set, Read, -1);
900
  return GetError(set, Write);
901
}
902

903
int RegisterContextDarwin_riscv32::WriteCSR() {
904
  int set = CSRRegSet;
905
  if (!RegisterSetIsCached(set)) {
906
    SetError(set, Write, -1);
907
    return -1;
908
  }
909
  SetError(set, Write, DoWriteCSR(GetThreadID(), set, csr));
910
  SetError(set, Read, -1);
911
  return GetError(set, Write);
912
}
913

914
int RegisterContextDarwin_riscv32::ReadRegisterSet(uint32_t set, bool force) {
915
  switch (set) {
916
  case GPRRegSet:
917
    return ReadGPR(force);
918
  case FPURegSet:
919
    return ReadFPU(force);
920
  case EXCRegSet:
921
    return ReadEXC(force);
922
  case CSRRegSet:
923
    return ReadCSR(force);
924
  default:
925
    break;
926
  }
927
  return -1;
928
}
929

930
int RegisterContextDarwin_riscv32::WriteRegisterSet(uint32_t set) {
931
  // Make sure we have a valid context to set.
932
  if (RegisterSetIsCached(set)) {
933
    switch (set) {
934
    case GPRRegSet:
935
      return WriteGPR();
936
    case FPURegSet:
937
      return WriteFPU();
938
    case EXCRegSet:
939
      return WriteEXC();
940
    case CSRRegSet:
941
      return WriteCSR();
942
    default:
943
      break;
944
    }
945
  }
946
  return -1;
947
}
948

949
bool RegisterContextDarwin_riscv32::ReadRegister(const RegisterInfo *reg_info,
950
                                                 RegisterValue &value) {
951
  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
952
  int set = RegisterContextDarwin_riscv32::GetSetForNativeRegNum(reg);
953

954
  if (set == -1)
955
    return false;
956

957
  if (ReadRegisterSet(set, false) != 0)
958
    return false;
959

960
  switch (reg) {
961
  case gpr_x0:
962
  case gpr_x1:
963
  case gpr_x2:
964
  case gpr_x3:
965
  case gpr_x4:
966
  case gpr_x5:
967
  case gpr_x6:
968
  case gpr_x7:
969
  case gpr_x8:
970
  case gpr_x9:
971
  case gpr_x10:
972
  case gpr_x11:
973
  case gpr_x12:
974
  case gpr_x13:
975
  case gpr_x14:
976
  case gpr_x15:
977
  case gpr_x16:
978
  case gpr_x17:
979
  case gpr_x18:
980
  case gpr_x19:
981
  case gpr_x20:
982
  case gpr_x21:
983
  case gpr_x22:
984
  case gpr_x23:
985
  case gpr_x24:
986
  case gpr_x25:
987
  case gpr_x26:
988
  case gpr_x27:
989
  case gpr_x28:
990
  case gpr_x29:
991
  case gpr_x30:
992
  case gpr_x31:
993
  case gpr_pc:
994
    value = (&gpr.x0)[reg - gpr_x0];
995
    break;
996

997
  case fpr_f0:
998
  case fpr_f1:
999
  case fpr_f2:
1000
  case fpr_f3:
1001
  case fpr_f4:
1002
  case fpr_f5:
1003
  case fpr_f6:
1004
  case fpr_f7:
1005
  case fpr_f8:
1006
  case fpr_f9:
1007
  case fpr_f10:
1008
  case fpr_f11:
1009
  case fpr_f12:
1010
  case fpr_f13:
1011
  case fpr_f14:
1012
  case fpr_f15:
1013
  case fpr_f16:
1014
  case fpr_f17:
1015
  case fpr_f18:
1016
  case fpr_f19:
1017
  case fpr_f20:
1018
  case fpr_f21:
1019
  case fpr_f22:
1020
  case fpr_f23:
1021
  case fpr_f24:
1022
  case fpr_f25:
1023
  case fpr_f26:
1024
  case fpr_f27:
1025
  case fpr_f28:
1026
  case fpr_f29:
1027
  case fpr_f30:
1028
  case fpr_f31:
1029
  case fpr_fcsr:
1030
    value = (&fpr.f0)[reg - fpr_f0];
1031
    break;
1032

1033
  case exc_exception:
1034
    value = exc.exception;
1035
    break;
1036

1037
  case exc_fsr:
1038
    value = exc.fsr;
1039
    break;
1040

1041
  case exc_far:
1042
    value = exc.far;
1043
    break;
1044

1045
  case csr_bank:
1046
    // These values don't fit into scalar types,
1047
    // RegisterContext::ReadRegisterBytes() must be used for these registers
1048
    //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes,
1049
    // 10);
1050

1051
    // AArch64 copies NEON registers with
1052
    // value.SetBytes(csr.bytes, reg_info->byte_size,
1053
    //                endian::InlHostByteOrder());
1054
    return false;
1055

1056
  default:
1057
    return false;
1058
  }
1059
  return true;
1060
}
1061

1062
bool RegisterContextDarwin_riscv32::WriteRegister(const RegisterInfo *reg_info,
1063
                                                  const RegisterValue &value) {
1064
  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
1065
  int set = GetSetForNativeRegNum(reg);
1066

1067
  if (set == -1)
1068
    return false;
1069

1070
  if (ReadRegisterSet(set, false) != 0)
1071
    return false;
1072

1073
  switch (reg) {
1074
  case gpr_x0:
1075
  case gpr_x1:
1076
  case gpr_x2:
1077
  case gpr_x3:
1078
  case gpr_x4:
1079
  case gpr_x5:
1080
  case gpr_x6:
1081
  case gpr_x7:
1082
  case gpr_x8:
1083
  case gpr_x9:
1084
  case gpr_x10:
1085
  case gpr_x11:
1086
  case gpr_x12:
1087
  case gpr_x13:
1088
  case gpr_x14:
1089
  case gpr_x15:
1090
  case gpr_x16:
1091
  case gpr_x17:
1092
  case gpr_x18:
1093
  case gpr_x19:
1094
  case gpr_x20:
1095
  case gpr_x21:
1096
  case gpr_x22:
1097
  case gpr_x23:
1098
  case gpr_x24:
1099
  case gpr_x25:
1100
  case gpr_x26:
1101
  case gpr_x27:
1102
  case gpr_x28:
1103
  case gpr_x29:
1104
  case gpr_x30:
1105
  case gpr_x31:
1106
  case gpr_pc:
1107
    (&gpr.x0)[reg - gpr_x0] = value.GetAsUInt32();
1108
    break;
1109

1110
  case fpr_f0:
1111
  case fpr_f1:
1112
  case fpr_f2:
1113
  case fpr_f3:
1114
  case fpr_f4:
1115
  case fpr_f5:
1116
  case fpr_f6:
1117
  case fpr_f7:
1118
  case fpr_f8:
1119
  case fpr_f9:
1120
  case fpr_f10:
1121
  case fpr_f11:
1122
  case fpr_f12:
1123
  case fpr_f13:
1124
  case fpr_f14:
1125
  case fpr_f15:
1126
  case fpr_f16:
1127
  case fpr_f17:
1128
  case fpr_f18:
1129
  case fpr_f19:
1130
  case fpr_f20:
1131
  case fpr_f21:
1132
  case fpr_f22:
1133
  case fpr_f23:
1134
  case fpr_f24:
1135
  case fpr_f25:
1136
  case fpr_f26:
1137
  case fpr_f27:
1138
  case fpr_f28:
1139
  case fpr_f29:
1140
  case fpr_f30:
1141
  case fpr_f31:
1142
  case fpr_fcsr:
1143
    (&fpr.f0)[reg - fpr_f0] = value.GetAsUInt32();
1144
    break;
1145

1146
  case exc_exception:
1147
    exc.exception = value.GetAsUInt32();
1148
    break;
1149

1150
  case exc_fsr:
1151
    exc.fsr = value.GetAsUInt32();
1152
    break;
1153

1154
  case exc_far:
1155
    exc.far = value.GetAsUInt32();
1156
    break;
1157

1158
  case csr_bank:
1159
    // These values don't fit into scalar types,
1160
    // RegisterContext::ReadRegisterBytes() must be used for these registers
1161
    //::memcpy(csr.bytes, value.GetBytes(),
1162
    // value.GetByteSize());
1163
    return false;
1164

1165
  default:
1166
    return false;
1167
  }
1168
  return WriteRegisterSet(set) == 0;
1169
}
1170

1171
bool RegisterContextDarwin_riscv32::ReadAllRegisterValues(
1172
    lldb::WritableDataBufferSP &data_sp) {
1173
  data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
1174
  if (ReadGPR(false) == 0 && ReadFPU(false) == 0 && ReadEXC(false) == 0 &&
1175
      ReadCSR(false) == 0) {
1176
    uint8_t *dst = data_sp->GetBytes();
1177
    ::memcpy(dst, &gpr, sizeof(gpr));
1178
    dst += sizeof(gpr);
1179

1180
    ::memcpy(dst, &fpr, sizeof(fpr));
1181
    dst += sizeof(gpr);
1182

1183
    ::memcpy(dst, &exc, sizeof(exc));
1184
    return true;
1185

1186
    ::memcpy(dst, &csr, sizeof(csr));
1187
    return true;
1188
  }
1189
  return false;
1190
}
1191

1192
bool RegisterContextDarwin_riscv32::WriteAllRegisterValues(
1193
    const lldb::DataBufferSP &data_sp) {
1194
  if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
1195
    const uint8_t *src = data_sp->GetBytes();
1196
    ::memcpy(&gpr, src, sizeof(gpr));
1197
    src += sizeof(gpr);
1198

1199
    ::memcpy(&fpr, src, sizeof(fpr));
1200
    src += sizeof(fpr);
1201

1202
    ::memcpy(&exc, src, sizeof(exc));
1203
    src += sizeof(exc);
1204

1205
    ::memcpy(&csr, src, sizeof(csr));
1206
    uint32_t success_count = 0;
1207

1208
    if (WriteGPR() == 0)
1209
      ++success_count;
1210
    if (WriteFPU() == 0)
1211
      ++success_count;
1212
    if (WriteEXC() == 0)
1213
      ++success_count;
1214
    if (WriteCSR() == 0)
1215
      ++success_count;
1216
    return success_count == 3;
1217
  }
1218
  return false;
1219
}
1220

1221
uint32_t RegisterContextDarwin_riscv32::ConvertRegisterKindToRegisterNumber(
1222
    lldb::RegisterKind kind, uint32_t reg) {
1223
  if (kind == eRegisterKindGeneric) {
1224
    switch (reg) {
1225
    case LLDB_REGNUM_GENERIC_PC:
1226
      return gpr_pc;
1227
    case LLDB_REGNUM_GENERIC_SP:
1228
      return gpr_x2;
1229
    case LLDB_REGNUM_GENERIC_FP:
1230
      return gpr_x8;
1231
    case LLDB_REGNUM_GENERIC_RA:
1232
      return gpr_x1;
1233
    default:
1234
      break;
1235
    }
1236
  } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
1237
    switch (reg) {
1238
    case riscv_dwarf::dwarf_gpr_x0:
1239
    case riscv_dwarf::dwarf_gpr_x1:
1240
    case riscv_dwarf::dwarf_gpr_x2:
1241
    case riscv_dwarf::dwarf_gpr_x3:
1242
    case riscv_dwarf::dwarf_gpr_x4:
1243
    case riscv_dwarf::dwarf_gpr_x5:
1244
    case riscv_dwarf::dwarf_gpr_x6:
1245
    case riscv_dwarf::dwarf_gpr_x7:
1246
    case riscv_dwarf::dwarf_gpr_x8:
1247
    case riscv_dwarf::dwarf_gpr_x9:
1248
    case riscv_dwarf::dwarf_gpr_x10:
1249
    case riscv_dwarf::dwarf_gpr_x11:
1250
    case riscv_dwarf::dwarf_gpr_x12:
1251
    case riscv_dwarf::dwarf_gpr_x13:
1252
    case riscv_dwarf::dwarf_gpr_x14:
1253
    case riscv_dwarf::dwarf_gpr_x15:
1254
    case riscv_dwarf::dwarf_gpr_x16:
1255
    case riscv_dwarf::dwarf_gpr_x17:
1256
    case riscv_dwarf::dwarf_gpr_x18:
1257
    case riscv_dwarf::dwarf_gpr_x19:
1258
    case riscv_dwarf::dwarf_gpr_x20:
1259
    case riscv_dwarf::dwarf_gpr_x21:
1260
    case riscv_dwarf::dwarf_gpr_x22:
1261
    case riscv_dwarf::dwarf_gpr_x23:
1262
    case riscv_dwarf::dwarf_gpr_x24:
1263
    case riscv_dwarf::dwarf_gpr_x25:
1264
    case riscv_dwarf::dwarf_gpr_x26:
1265
    case riscv_dwarf::dwarf_gpr_x27:
1266
    case riscv_dwarf::dwarf_gpr_x28:
1267
    case riscv_dwarf::dwarf_gpr_x29:
1268
    case riscv_dwarf::dwarf_gpr_x30:
1269
    case riscv_dwarf::dwarf_gpr_x31:
1270
      return gpr_x0 + (reg - riscv_dwarf::dwarf_gpr_x0);
1271

1272
    case riscv_dwarf::dwarf_fpr_f0:
1273
    case riscv_dwarf::dwarf_fpr_f1:
1274
    case riscv_dwarf::dwarf_fpr_f2:
1275
    case riscv_dwarf::dwarf_fpr_f3:
1276
    case riscv_dwarf::dwarf_fpr_f4:
1277
    case riscv_dwarf::dwarf_fpr_f5:
1278
    case riscv_dwarf::dwarf_fpr_f6:
1279
    case riscv_dwarf::dwarf_fpr_f7:
1280
    case riscv_dwarf::dwarf_fpr_f8:
1281
    case riscv_dwarf::dwarf_fpr_f9:
1282
    case riscv_dwarf::dwarf_fpr_f10:
1283
    case riscv_dwarf::dwarf_fpr_f11:
1284
    case riscv_dwarf::dwarf_fpr_f12:
1285
    case riscv_dwarf::dwarf_fpr_f13:
1286
    case riscv_dwarf::dwarf_fpr_f14:
1287
    case riscv_dwarf::dwarf_fpr_f15:
1288
    case riscv_dwarf::dwarf_fpr_f16:
1289
    case riscv_dwarf::dwarf_fpr_f17:
1290
    case riscv_dwarf::dwarf_fpr_f18:
1291
    case riscv_dwarf::dwarf_fpr_f19:
1292
    case riscv_dwarf::dwarf_fpr_f20:
1293
    case riscv_dwarf::dwarf_fpr_f21:
1294
    case riscv_dwarf::dwarf_fpr_f22:
1295
    case riscv_dwarf::dwarf_fpr_f23:
1296
    case riscv_dwarf::dwarf_fpr_f24:
1297
    case riscv_dwarf::dwarf_fpr_f25:
1298
    case riscv_dwarf::dwarf_fpr_f26:
1299
    case riscv_dwarf::dwarf_fpr_f27:
1300
    case riscv_dwarf::dwarf_fpr_f28:
1301
    case riscv_dwarf::dwarf_fpr_f29:
1302
    case riscv_dwarf::dwarf_fpr_f30:
1303
    case riscv_dwarf::dwarf_fpr_f31:
1304
      return fpr_f0 + (reg - riscv_dwarf::dwarf_fpr_f0);
1305

1306
    default:
1307
      break;
1308
    }
1309
  } else if (kind == eRegisterKindLLDB) {
1310
    return reg;
1311
  }
1312
  return LLDB_INVALID_REGNUM;
1313
}
1314

1315
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