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GitHub Repository: hrydgard/ppsspp
 Path: blob/master/Common/CPUDetect.h
Views: 1401
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// Copyright (C) 2003 Dolphin Project.

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// This program is free software: you can redistribute it and/or modify

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// it under the terms of the GNU General Public License as published by

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// the Free Software Foundation, version 2.0.

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// This program is distributed in the hope that it will be useful,

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// but WITHOUT ANY WARRANTY; without even the implied warranty of

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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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// GNU General Public License 2.0 for more details.

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// A copy of the GPL 2.0 should have been included with the program.

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// If not, see http://www.gnu.org/licenses/

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// Official SVN repository and contact information can be found at

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// http://code.google.com/p/dolphin-emu/

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// Detect the cpu, so we'll know which optimizations to use

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#pragma once

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#include "ppsspp_config.h"

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#include <string>

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#include <vector>

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enum CPUVendor {

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	VENDOR_INTEL = 0,

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	VENDOR_AMD = 1,

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	VENDOR_ARM = 2,

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	VENDOR_OTHER = 3,

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};

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struct CPUInfo {

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	CPUVendor vendor;

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	// Misc

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	char cpu_string[0x21];

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	char brand_string[0x41];

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	bool OS64bit;

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	bool CPU64bit;

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	bool Mode64bit;

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	bool HTT;

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	// Number of real CPU cores.

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	int num_cores;

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	// Number of logical CPUs per core.

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	int logical_cpu_count;

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	bool bAtom;

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	bool bPOPCNT;

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	bool bLAHFSAHF64;

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	bool bLongMode;

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	bool bMOVBE;

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	bool bFXSR;

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	bool bLZCNT;

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	bool bBMI1;

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	bool bBMI2;

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	bool bBMI2_fast;

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	bool bXOP;

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	bool bRTM;

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	// x86 : SIMD 128 bit

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	bool bSSE;

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	bool bSSE2;

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	bool bSSE3;

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	bool bSSSE3;

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	bool bSSE4_1;

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	bool bSSE4_2;

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	bool bSSE4A;

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	bool bAES;

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	bool bSHA;

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	bool bF16C;

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	// x86 : SIMD 256 bit

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	bool bAVX;

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	bool bAVX2;

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	bool bFMA3;

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	bool bFMA4;

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	// ARM specific CPUInfo

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	bool bSwp;

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	bool bHalf;

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	bool bThumb;

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	bool bFastMult;

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	bool bVFP;

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	bool bEDSP;

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	bool bThumbEE;

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	bool bNEON;

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	bool bVFPv3;

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	bool bTLS;

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	bool bVFPv4;

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	bool bIDIVa;

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	bool bIDIVt;

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	// ARMv8 specific

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	bool bFP;

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	bool bASIMD;

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	bool bSVE;

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	bool bSVE2;

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	bool bFRINT;

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	// MIPS specific

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	bool bXBurst1;

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	bool bXBurst2;

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	// RiscV specific extension flags.

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	bool RiscV_M;

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	bool RiscV_A;

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	bool RiscV_F;

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	bool RiscV_D;

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	bool RiscV_C;

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	bool RiscV_V;

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	bool RiscV_Zicsr;

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	bool RiscV_Zba;

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	bool RiscV_Zbb;

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	bool RiscV_Zbc;

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	bool RiscV_Zbs;

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	bool RiscV_Zcb;

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	bool RiscV_Zfa;

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	bool RiscV_Zfh;

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	bool RiscV_Zfhmin;

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	bool RiscV_Zicond;

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	bool RiscV_Zvbb;

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	bool RiscV_Zvkb;

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	// LoongArch specific extension flags.

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	bool LOONGARCH_CPUCFG;

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	bool LOONGARCH_LAM;

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	bool LOONGARCH_UAL;

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	bool LOONGARCH_FPU;

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	bool LOONGARCH_LSX;

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	bool LOONGARCH_LASX;

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	bool LOONGARCH_CRC32;

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	bool LOONGARCH_COMPLEX;

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	bool LOONGARCH_CRYPTO;

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	bool LOONGARCH_LVZ;

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	bool LOONGARCH_LBT_X86;

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	bool LOONGARCH_LBT_ARM;

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	bool LOONGARCH_LBT_MIPS;

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	bool LOONGARCH_PTW;

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	// Quirks

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	struct {

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		// Samsung Galaxy S7 devices (Exynos 8890) have a big.LITTLE configuration where the cacheline size differs between big and LITTLE.

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		// GCC's cache clearing function would detect the cacheline size on one and keep it for later. When clearing

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		// with the wrong cacheline size on the other, that's an issue. In case we want to do something different in this

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		// situation in the future, let's keep this as a quirk, but our current code won't detect it reliably

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		// if it happens on new archs. We now use better clearing code on ARM64 that doesn't have this issue.

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		bool bExynos8890DifferingCachelineSizes;

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	} sQuirks;

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	// Call Detect()

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	explicit CPUInfo();

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	// Turn the cpu info into a string we can show

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	std::vector<std::string> Features();

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	std::string Summarize();

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private:

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	// Detects the various cpu features

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	void Detect();

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};

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extern CPUInfo cpu_info;

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const char *GetCompilerABI();

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