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Path: blob/master/Common/MachineContext.h
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// Copyright 2008 Dolphin Emulator Project1// Licensed under GPLv2+2// Refer to the license.txt file included.34// Note: If MACHINE_CONTEXT_SUPPORTED is not set after including this,5// there is no access to the context from exception handlers (and possibly no exception handling support).67#pragma once89#include "ppsspp_config.h"1011#if PPSSPP_PLATFORM(WINDOWS) && !PPSSPP_PLATFORM(UWP)1213#include <windows.h>14typedef CONTEXT SContext;1516#if defined(__LIBRETRO__)1718#elif PPSSPP_ARCH(AMD64)1920#define MACHINE_CONTEXT_SUPPORTED2122#define CTX_RAX Rax23#define CTX_RBX Rbx24#define CTX_RCX Rcx25#define CTX_RDX Rdx26#define CTX_RDI Rdi27#define CTX_RSI Rsi28#define CTX_RBP Rbp29#define CTX_RSP Rsp30#define CTX_R8 R831#define CTX_R9 R932#define CTX_R10 R1033#define CTX_R11 R1134#define CTX_R12 R1235#define CTX_R13 R1336#define CTX_R14 R1437#define CTX_R15 R1538#define CTX_RIP Rip3940#elif PPSSPP_ARCH(X86)4142#define MACHINE_CONTEXT_SUPPORTED4344#define CTX_RAX Eax45#define CTX_RBX Ebx46#define CTX_RCX Ecx47#define CTX_RDX Edx48#define CTX_RDI Edi49#define CTX_RSI Esi50#define CTX_RBP Ebp51#define CTX_RSP Esp52#define CTX_RIP Eip5354#elif PPSSPP_ARCH(ARM64)5556#define CTX_REG(x) X[x]57#define CTX_SP Sp58#define CTX_PC Pc5960#elif PPSSPP_ARCH(ARM)6162//#define CTX_REG(x) R##x63#define CTX_SP Sp64#define CTX_PC Pc6566#endif6768#elif PPSSPP_PLATFORM(MAC)6970// for modules:71#define _XOPEN_SOURCE72#include <ucontext.h>7374#include <mach/mach.h>75#include <mach/message.h>7677#if PPSSPP_ARCH(AMD64)7879#define MACHINE_CONTEXT_SUPPORTED8081typedef x86_thread_state64_t SContext;82#define CTX_RAX __rax83#define CTX_RBX __rbx84#define CTX_RCX __rcx85#define CTX_RDX __rdx86#define CTX_RDI __rdi87#define CTX_RSI __rsi88#define CTX_RBP __rbp89#define CTX_RSP __rsp90#define CTX_R8 __r891#define CTX_R9 __r992#define CTX_R10 __r1093#define CTX_R11 __r1194#define CTX_R12 __r1295#define CTX_R13 __r1396#define CTX_R14 __r1497#define CTX_R15 __r1598#define CTX_RIP __rip99100#else101102// No context definition for architecture103104#endif105106#elif defined(__linux__)107108#include <signal.h>109110#if PPSSPP_ARCH(AMD64)111112#include <ucontext.h>113typedef mcontext_t SContext;114115#define MACHINE_CONTEXT_SUPPORTED116117#define CTX_RAX gregs[REG_RAX]118#define CTX_RBX gregs[REG_RBX]119#define CTX_RCX gregs[REG_RCX]120#define CTX_RDX gregs[REG_RDX]121#define CTX_RDI gregs[REG_RDI]122#define CTX_RSI gregs[REG_RSI]123#define CTX_RBP gregs[REG_RBP]124#define CTX_RSP gregs[REG_RSP]125#define CTX_R8 gregs[REG_R8]126#define CTX_R9 gregs[REG_R9]127#define CTX_R10 gregs[REG_R10]128#define CTX_R11 gregs[REG_R11]129#define CTX_R12 gregs[REG_R12]130#define CTX_R13 gregs[REG_R13]131#define CTX_R14 gregs[REG_R14]132#define CTX_R15 gregs[REG_R15]133#define CTX_RIP gregs[REG_RIP]134135#elif PPSSPP_ARCH(X86)136137#include <ucontext.h>138typedef mcontext_t SContext;139140#define MACHINE_CONTEXT_SUPPORTED141142#define CTX_RAX gregs[REG_EAX]143#define CTX_RBX gregs[REG_EBX]144#define CTX_RCX gregs[REG_ECX]145#define CTX_RDX gregs[REG_EDX]146#define CTX_RDI gregs[REG_EDI]147#define CTX_RSI gregs[REG_ESI]148#define CTX_RBP gregs[REG_EBP]149#define CTX_RSP gregs[REG_ESP]150#define CTX_RIP gregs[REG_EIP]151152#elif PPSSPP_ARCH(ARM64)153154#define MACHINE_CONTEXT_SUPPORTED155156typedef sigcontext SContext;157158#define CTX_REG(x) regs[x]159#define CTX_SP sp160#define CTX_PC pc161162#elif PPSSPP_ARCH(ARM)163164#define MACHINE_CONTEXT_SUPPORTED165166typedef sigcontext SContext;167#define CTX_PC arm_pc168#define CTX_REG(x) regs[x]169170#elif PPSSPP_ARCH(RISCV64)171172#include <ucontext.h>173typedef mcontext_t SContext;174175#define MACHINE_CONTEXT_SUPPORTED176177#define CTX_REG(x) __gregs[x]178#define CTX_PC CTX_REG(0)179#define CTX_SP CTX_REG(2)180181#else182183// No context definition for architecture184185#endif186187#elif defined(__OpenBSD__)188189#if PPSSPP_ARCH(AMD64)190191#include <signal.h>192typedef ucontext_t SContext;193194#define MACHINE_CONTEXT_SUPPORTED195196#define CTX_RAX sc_rax197#define CTX_RBX sc_rbx198#define CTX_RCX sc_rcx199#define CTX_RDX sc_rdx200#define CTX_RDI sc_rdi201#define CTX_RSI sc_rsi202#define CTX_RBP sc_rbp203#define CTX_RSP sc_rsp204#define CTX_R8 sc_r8205#define CTX_R9 sc_r9206#define CTX_R10 sc_r10207#define CTX_R11 sc_r11208#define CTX_R12 sc_r12209#define CTX_R13 sc_r13210#define CTX_R14 sc_r14211#define CTX_R15 sc_r15212#define CTX_RIP sc_rip213214#else215216// No context definition for architecture217218#endif219220#elif defined(__NetBSD__)221222#if PPSSPP_ARCH(AMD64)223224#include <ucontext.h>225typedef mcontext_t SContext;226227#define MACHINE_CONTEXT_SUPPORTED228229#define CTX_RAX __gregs[_REG_RAX]230#define CTX_RBX __gregs[_REG_RBX]231#define CTX_RCX __gregs[_REG_RCX]232#define CTX_RDX __gregs[_REG_RDX]233#define CTX_RDI __gregs[_REG_RDI]234#define CTX_RSI __gregs[_REG_RSI]235#define CTX_RBP __gregs[_REG_RBP]236#define CTX_RSP __gregs[_REG_RSP]237#define CTX_R8 __gregs[_REG_R8]238#define CTX_R9 __gregs[_REG_R9]239#define CTX_R10 __gregs[_REG_R10]240#define CTX_R11 __gregs[_REG_R11]241#define CTX_R12 __gregs[_REG_R12]242#define CTX_R13 __gregs[_REG_R13]243#define CTX_R14 __gregs[_REG_R14]244#define CTX_R15 __gregs[_REG_R15]245#define CTX_RIP __gregs[_REG_RIP]246247#else248249// No context definition for architecture250251#endif252253#elif defined(__FreeBSD__)254255#if PPSSPP_ARCH(AMD64)256257#include <ucontext.h>258typedef mcontext_t SContext;259260#define MACHINE_CONTEXT_SUPPORTED261262#define CTX_RAX mc_rax263#define CTX_RBX mc_rbx264#define CTX_RCX mc_rcx265#define CTX_RDX mc_rdx266#define CTX_RDI mc_rdi267#define CTX_RSI mc_rsi268#define CTX_RBP mc_rbp269#define CTX_RSP mc_rsp270#define CTX_R8 mc_r8271#define CTX_R9 mc_r9272#define CTX_R10 mc_r10273#define CTX_R11 mc_r11274#define CTX_R12 mc_r12275#define CTX_R13 mc_r13276#define CTX_R14 mc_r14277#define CTX_R15 mc_r15278#define CTX_RIP mc_rip279280#else281282// No context definition for architecture283284#endif285286#elif defined(__HAIKU__)287288#if PPSSPP_ARCH(AMD64)289290#include <signal.h>291typedef mcontext_t SContext;292293#define MACHINE_CONTEXT_SUPPORTED294295#define CTX_RAX rax296#define CTX_RBX rbx297#define CTX_RCX rcx298#define CTX_RDX rdx299#define CTX_RDI rdi300#define CTX_RSI rsi301#define CTX_RBP rbp302#define CTX_RSP rsp303#define CTX_R8 r8304#define CTX_R9 r9305#define CTX_R10 r10306#define CTX_R11 r11307#define CTX_R12 r12308#define CTX_R13 r13309#define CTX_R14 r14310#define CTX_R15 r15311#define CTX_RIP rip312313#else314315// No context definition for machine316317#endif318319#else320321// No context definition for OS322323#endif324325#ifdef MACHINE_CONTEXT_SUPPORTED326327#if PPSSPP_ARCH(AMD64)328329#include <cstdint>330#include <stddef.h>331#define CTX_PC CTX_RIP332static inline uint64_t *ContextRN(SContext* ctx, int n) {333static const uint8_t offsets[] = {334offsetof(SContext, CTX_RAX), offsetof(SContext, CTX_RCX), offsetof(SContext, CTX_RDX),335offsetof(SContext, CTX_RBX), offsetof(SContext, CTX_RSP), offsetof(SContext, CTX_RBP),336offsetof(SContext, CTX_RSI), offsetof(SContext, CTX_RDI), offsetof(SContext, CTX_R8),337offsetof(SContext, CTX_R9), offsetof(SContext, CTX_R10), offsetof(SContext, CTX_R11),338offsetof(SContext, CTX_R12), offsetof(SContext, CTX_R13), offsetof(SContext, CTX_R14),339offsetof(SContext, CTX_R15)};340return (uint64_t *)((char *)ctx + offsets[n]);341}342343#elif PPSSPP_ARCH(X86)344345#include <cstdint>346#include <stddef.h>347#define CTX_PC CTX_RIP348349static inline uint32_t *ContextRN(SContext* ctx, int n) {350static const uint8_t offsets[] = {351offsetof(SContext, CTX_RAX), offsetof(SContext, CTX_RCX), offsetof(SContext, CTX_RDX),352offsetof(SContext, CTX_RBX), offsetof(SContext, CTX_RSP), offsetof(SContext, CTX_RBP),353offsetof(SContext, CTX_RSI), offsetof(SContext, CTX_RDI)};354return (uint32_t *)((char*)ctx + offsets[n]);355}356357#endif // arch358359#endif // MACHINE_CONTEXT_SUPPORTED360361362