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Path: blob/master/Core/MIPS/ARM/ArmCompVFPUNEON.cpp
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// Copyright (c) 2013- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617// NEON VFPU18// This is where we will create an alternate implementation of the VFPU emulation19// that uses NEON Q registers to cache pairs/tris/quads, and so on.20// Will require major extensions to the reg cache and other things.2122// ARM NEON can only do pairs and quads, not tris and scalars.23// We can do scalars, though, for many operations if all the operands24// are below Q8 (D16, S32) using regular VFP instructions but really not sure25// if it's worth it.2627#include "ppsspp_config.h"28#if PPSSPP_ARCH(ARM)2930#include <cmath>3132#include "Common/Data/Convert/SmallDataConvert.h"33#include "Common/Math/math_util.h"3435#include "Common/CPUDetect.h"36#include "Core/MemMap.h"37#include "Core/MIPS/MIPS.h"38#include "Core/MIPS/MIPSAnalyst.h"39#include "Core/MIPS/MIPSCodeUtils.h"40#include "Core/MIPS/MIPSVFPUUtils.h"41#include "Core/Config.h"42#include "Core/Reporting.h"4344#include "Core/MIPS/ARM/ArmJit.h"45#include "Core/MIPS/ARM/ArmRegCache.h"46#include "Core/MIPS/ARM/ArmRegCacheFPU.h"47#include "Core/MIPS/ARM/ArmCompVFPUNEONUtil.h"4849// TODO: Somehow #ifdef away on ARMv5eabi, without breaking the linker.5051// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.52// Currently known non working ones should have DISABLE.5354// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }55#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }56#define DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }57#define DISABLE_UNKNOWN_PREFIX { WARN_LOG(Log::JIT, "DISABLE: Unknown Prefix in %s", __FUNCTION__); fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }5859#define _RS MIPS_GET_RS(op)60#define _RT MIPS_GET_RT(op)61#define _RD MIPS_GET_RD(op)62#define _FS MIPS_GET_FS(op)63#define _FT MIPS_GET_FT(op)64#define _FD MIPS_GET_FD(op)65#define _SA MIPS_GET_SA(op)66#define _POS ((op>> 6) & 0x1F)67#define _SIZE ((op>>11) & 0x1F)68#define _IMM16 (signed short)(op & 0xFFFF)69#define _IMM26 (op & 0x03FFFFFF)707172namespace MIPSComp {7374using namespace ArmGen;75using namespace ArmJitConstants;7677static const float minus_one = -1.0f;78static const float one = 1.0f;79static const float zero = 0.0f;808182void ArmJit::CompNEON_VecDo3(MIPSOpcode op) {83CONDITIONAL_DISABLE(VFPU_VEC);84if (js.HasUnknownPrefix()) {85DISABLE_UNKNOWN_PREFIX;86}8788VectorSize sz = GetVecSize(op);89int n = GetNumVectorElements(sz);9091MappedRegs r = NEONMapDirtyInIn(op, sz, sz, sz);92ARMReg temp = MatchSize(Q0, r.vs);93// TODO: Special case for scalar94switch (op >> 26) {95case 24: //VFPU096switch ((op >> 23) & 7) {97case 0: VADD(F_32, r.vd, r.vs, r.vt); break; // vadd98case 1: VSUB(F_32, r.vd, r.vs, r.vt); break; // vsub99case 7: // vdiv // vdiv THERE IS NO NEON SIMD VDIV :( There's a fast reciprocal iterator thing though.100{101// Implement by falling back to VFP102VMOV(D0, D_0(r.vs));103VMOV(D1, D_0(r.vt));104VDIV(S0, S0, S2);105if (sz >= V_Pair)106VDIV(S1, S1, S3);107VMOV(D_0(r.vd), D0);108if (sz >= V_Triple) {109VMOV(D0, D_1(r.vs));110VMOV(D1, D_1(r.vt));111VDIV(S0, S0, S2);112if (sz == V_Quad)113VDIV(S1, S1, S3);114VMOV(D_1(r.vd), D0);115}116}117break;118default:119DISABLE;120}121break;122case 25: //VFPU1123switch ((op >> 23) & 7) {124case 0: VMUL(F_32, r.vd, r.vs, r.vt); break; // vmul125default:126DISABLE;127}128break;129case 27: //VFPU3130switch ((op >> 23) & 7) {131case 2: VMIN(F_32, r.vd, r.vs, r.vt); break; // vmin132case 3: VMAX(F_32, r.vd, r.vs, r.vt); break; // vmax133case 6: // vsge134VMOV_immf(temp, 1.0f);135VCGE(F_32, r.vd, r.vs, r.vt);136VAND(r.vd, r.vd, temp);137break;138case 7: // vslt139VMOV_immf(temp, 1.0f);140VCLT(F_32, r.vd, r.vs, r.vt);141VAND(r.vd, r.vd, temp);142break;143}144break;145146default:147DISABLE;148}149150NEONApplyPrefixD(r.vd);151152fpr.ReleaseSpillLocksAndDiscardTemps();153}154155156// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }157158void ArmJit::CompNEON_SV(MIPSOpcode op) {159CONDITIONAL_DISABLE(LSU_VFPU);160CheckMemoryBreakpoint();161162// Remember to use single lane stores here and not VLDR/VSTR - switching usage163// between NEON and VFPU can be expensive on some chips.164165// Here's a common idiom we should optimize:166// lv.s S200, 0(s4)167// lv.s S201, 4(s4)168// lv.s S202, 8(s4)169// vone.s S203170// vtfm4.q C000, E600, C200171// Would be great if we could somehow combine the lv.s into one vector instead of mapping three172// separate quads.173174s32 offset = (signed short)(op & 0xFFFC);175int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);176MIPSGPReg rs = _RS;177178bool doCheck = false;179switch (op >> 26)180{181case 50: //lv.s // VI(vt) = Memory::Read_U32(addr);182{183if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) {184INFO_LOG(Log::HLE, "LV.S fastmode!");185// TODO: Also look forward and combine multiple loads.186gpr.MapRegAsPointer(rs);187ARMReg ar = fpr.QMapReg(vt, V_Single, MAP_NOINIT | MAP_DIRTY);188if (offset) {189ADDI2R(R0, gpr.RPtr(rs), offset, R1);190VLD1_lane(F_32, ar, R0, 0, true);191} else {192VLD1_lane(F_32, ar, gpr.RPtr(rs), 0, true);193}194break;195}196INFO_LOG(Log::HLE, "LV.S slowmode!");197198// CC might be set by slow path below, so load regs first.199ARMReg ar = fpr.QMapReg(vt, V_Single, MAP_DIRTY | MAP_NOINIT);200if (gpr.IsImm(rs)) {201u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;202gpr.SetRegImm(R0, addr + (u32)Memory::base);203} else {204gpr.MapReg(rs);205if (g_Config.bFastMemory) {206SetR0ToEffectiveAddress(rs, offset);207} else {208SetCCAndR0ForSafeAddress(rs, offset, R1);209doCheck = true;210}211ADD(R0, R0, MEMBASEREG);212}213FixupBranch skip;214if (doCheck) {215skip = B_CC(CC_EQ);216}217VLD1_lane(F_32, ar, R0, 0, true);218if (doCheck) {219SetJumpTarget(skip);220SetCC(CC_AL);221}222}223break;224225case 58: //sv.s // Memory::Write_U32(VI(vt), addr);226{227if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) {228INFO_LOG(Log::HLE, "SV.S fastmode!");229// TODO: Also look forward and combine multiple stores.230gpr.MapRegAsPointer(rs);231ARMReg ar = fpr.QMapReg(vt, V_Single, 0);232if (offset) {233ADDI2R(R0, gpr.RPtr(rs), offset, R1);234VST1_lane(F_32, ar, R0, 0, true);235} else {236VST1_lane(F_32, ar, gpr.RPtr(rs), 0, true);237}238break;239}240241INFO_LOG(Log::HLE, "SV.S slowmode!");242// CC might be set by slow path below, so load regs first.243ARMReg ar = fpr.QMapReg(vt, V_Single, 0);244if (gpr.IsImm(rs)) {245u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;246gpr.SetRegImm(R0, addr + (u32)Memory::base);247} else {248gpr.MapReg(rs);249if (g_Config.bFastMemory) {250SetR0ToEffectiveAddress(rs, offset);251} else {252SetCCAndR0ForSafeAddress(rs, offset, R1);253doCheck = true;254}255ADD(R0, R0, MEMBASEREG);256}257FixupBranch skip;258if (doCheck) {259skip = B_CC(CC_EQ);260}261VST1_lane(F_32, ar, R0, 0, true);262if (doCheck) {263SetJumpTarget(skip);264SetCC(CC_AL);265}266}267break;268}269fpr.ReleaseSpillLocksAndDiscardTemps();270}271272inline int MIPS_GET_VQVT(u32 op) {273return (((op >> 16) & 0x1f)) | ((op & 1) << 5);274}275276void ArmJit::CompNEON_SVQ(MIPSOpcode op) {277CONDITIONAL_DISABLE(LSU_VFPU);278CheckMemoryBreakpoint();279280int offset = (signed short)(op & 0xFFFC);281int vt = MIPS_GET_VQVT(op.encoding);282MIPSGPReg rs = _RS;283bool doCheck = false;284switch (op >> 26)285{286case 54: //lv.q287{288// Check for four-in-a-row289const u32 ops[4] = {290op.encoding,291GetOffsetInstruction(1).encoding,292GetOffsetInstruction(2).encoding,293GetOffsetInstruction(3).encoding,294};295if (g_Config.bFastMemory && (ops[1] >> 26) == 54 && (ops[2] >> 26) == 54 && (ops[3] >> 26) == 54) {296int offsets[4] = {offset, (s16)(ops[1] & 0xFFFC), (s16)(ops[2] & 0xFFFC), (s16)(ops[3] & 0xFFFC)};297int rss[4] = {MIPS_GET_RS(op), MIPS_GET_RS(ops[1]), MIPS_GET_RS(ops[2]), MIPS_GET_RS(ops[3])};298if (offsets[1] == offset + 16 && offsets[2] == offsets[1] + 16 && offsets[3] == offsets[2] + 16 &&299rss[0] == rss[1] && rss[1] == rss[2] && rss[2] == rss[3]) {300int vts[4] = {MIPS_GET_VQVT(op.encoding), MIPS_GET_VQVT(ops[1]), MIPS_GET_VQVT(ops[2]), MIPS_GET_VQVT(ops[3])};301// TODO: Also check the destination registers!302// Detected four consecutive ones!303// gpr.MapRegAsPointer(rs);304// fpr.QLoad4x4(vts[4], rs, offset);305INFO_LOG(Log::JIT, "Matrix load detected! TODO: optimize");306// break;307}308}309310if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && offset < 0x400-16 && offset > -0x400-16) {311gpr.MapRegAsPointer(rs);312ARMReg ar = fpr.QMapReg(vt, V_Quad, MAP_DIRTY | MAP_NOINIT);313if (offset) {314ADDI2R(R0, gpr.RPtr(rs), offset, R1);315VLD1(F_32, ar, R0, 2, ALIGN_128);316} else {317VLD1(F_32, ar, gpr.RPtr(rs), 2, ALIGN_128);318}319break;320}321322// CC might be set by slow path below, so load regs first.323ARMReg ar = fpr.QMapReg(vt, V_Quad, MAP_DIRTY | MAP_NOINIT);324if (gpr.IsImm(rs)) {325u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;326gpr.SetRegImm(R0, addr + (u32)Memory::base);327} else {328gpr.MapReg(rs);329if (g_Config.bFastMemory) {330SetR0ToEffectiveAddress(rs, offset);331} else {332SetCCAndR0ForSafeAddress(rs, offset, R1);333doCheck = true;334}335ADD(R0, R0, MEMBASEREG);336}337338FixupBranch skip;339if (doCheck) {340skip = B_CC(CC_EQ);341}342343VLD1(F_32, ar, R0, 2, ALIGN_128);344345if (doCheck) {346SetJumpTarget(skip);347SetCC(CC_AL);348}349}350break;351352case 62: //sv.q353{354const u32 ops[4] = {355op.encoding,356GetOffsetInstruction(1).encoding,357GetOffsetInstruction(2).encoding,358GetOffsetInstruction(3).encoding,359};360if (g_Config.bFastMemory && (ops[1] >> 26) == 54 && (ops[2] >> 26) == 54 && (ops[3] >> 26) == 54) {361int offsets[4] = { offset, (s16)(ops[1] & 0xFFFC), (s16)(ops[2] & 0xFFFC), (s16)(ops[3] & 0xFFFC) };362int rss[4] = { MIPS_GET_RS(op), MIPS_GET_RS(ops[1]), MIPS_GET_RS(ops[2]), MIPS_GET_RS(ops[3]) };363if (offsets[1] == offset + 16 && offsets[2] == offsets[1] + 16 && offsets[3] == offsets[2] + 16 &&364rss[0] == rss[1] && rss[1] == rss[2] && rss[2] == rss[3]) {365int vts[4] = { MIPS_GET_VQVT(op.encoding), MIPS_GET_VQVT(ops[1]), MIPS_GET_VQVT(ops[2]), MIPS_GET_VQVT(ops[3]) };366// TODO: Also check the destination registers!367// Detected four consecutive ones!368// gpr.MapRegAsPointer(rs);369// fpr.QLoad4x4(vts[4], rs, offset);370INFO_LOG(Log::JIT, "Matrix store detected! TODO: optimize");371// break;372}373}374375if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && offset < 0x400-16 && offset > -0x400-16) {376gpr.MapRegAsPointer(rs);377ARMReg ar = fpr.QMapReg(vt, V_Quad, 0);378if (offset) {379ADDI2R(R0, gpr.RPtr(rs), offset, R1);380VST1(F_32, ar, R0, 2, ALIGN_128);381} else {382VST1(F_32, ar, gpr.RPtr(rs), 2, ALIGN_128);383}384break;385}386387// CC might be set by slow path below, so load regs first.388ARMReg ar = fpr.QMapReg(vt, V_Quad, 0);389390if (gpr.IsImm(rs)) {391u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;392gpr.SetRegImm(R0, addr + (u32)Memory::base);393} else {394gpr.MapReg(rs);395if (g_Config.bFastMemory) {396SetR0ToEffectiveAddress(rs, offset);397} else {398SetCCAndR0ForSafeAddress(rs, offset, R1);399doCheck = true;400}401ADD(R0, R0, MEMBASEREG);402}403404FixupBranch skip;405if (doCheck) {406skip = B_CC(CC_EQ);407}408409VST1(F_32, ar, R0, 2, ALIGN_128);410411if (doCheck) {412SetJumpTarget(skip);413SetCC(CC_AL);414}415}416break;417418default:419DISABLE;420break;421}422fpr.ReleaseSpillLocksAndDiscardTemps();423}424425void ArmJit::CompNEON_VVectorInit(MIPSOpcode op) {426CONDITIONAL_DISABLE(VFPU_XFER);427// WARNING: No prefix support!428if (js.HasUnknownPrefix()) {429DISABLE_UNKNOWN_PREFIX;430}431VectorSize sz = GetVecSize(op);432DestARMReg vd = NEONMapPrefixD(_VD, sz, MAP_NOINIT | MAP_DIRTY);433434switch ((op >> 16) & 0xF) {435case 6: // vzero436VEOR(vd.rd, vd.rd, vd.rd);437break;438case 7: // vone439VMOV_immf(vd.rd, 1.0f);440break;441default:442DISABLE;443break;444}445NEONApplyPrefixD(vd);446447fpr.ReleaseSpillLocksAndDiscardTemps();448}449450void ArmJit::CompNEON_VDot(MIPSOpcode op) {451CONDITIONAL_DISABLE(VFPU_VEC);452if (js.HasUnknownPrefix()) {453DISABLE_UNKNOWN_PREFIX;454}455456VectorSize sz = GetVecSize(op);457MappedRegs r = NEONMapDirtyInIn(op, V_Single, sz, sz);458459switch (sz) {460case V_Pair:461VMUL(F_32, r.vd, r.vs, r.vt);462VPADD(F_32, r.vd, r.vd, r.vd);463break;464case V_Triple:465VMUL(F_32, Q0, r.vs, r.vt);466VPADD(F_32, D0, D0, D0);467VADD(F_32, r.vd, D0, D1);468break;469case V_Quad:470VMUL(F_32, D0, D_0(r.vs), D_0(r.vt));471VMLA(F_32, D0, D_1(r.vs), D_1(r.vt));472VPADD(F_32, r.vd, D0, D0);473break;474case V_Single:475case V_Invalid:476;477}478479NEONApplyPrefixD(r.vd);480fpr.ReleaseSpillLocksAndDiscardTemps();481}482483484void ArmJit::CompNEON_VHdp(MIPSOpcode op) {485CONDITIONAL_DISABLE(VFPU_VEC);486if (js.HasUnknownPrefix()) {487DISABLE_UNKNOWN_PREFIX;488}489490DISABLE;491492// Similar to VDot but the last component is only s instead of s * t.493// A bit tricky on NEON...494}495496void ArmJit::CompNEON_VScl(MIPSOpcode op) {497CONDITIONAL_DISABLE(VFPU_VEC);498if (js.HasUnknownPrefix()) {499DISABLE_UNKNOWN_PREFIX;500}501502VectorSize sz = GetVecSize(op);503MappedRegs r = NEONMapDirtyInIn(op, sz, sz, V_Single);504505ARMReg temp = MatchSize(Q0, r.vt);506507// TODO: VMUL_scalar directly when possible508VMOV_neon(temp, r.vt);509VMUL_scalar(F_32, r.vd, r.vs, DScalar(Q0, 0));510511NEONApplyPrefixD(r.vd);512fpr.ReleaseSpillLocksAndDiscardTemps();513}514515void ArmJit::CompNEON_VV2Op(MIPSOpcode op) {516CONDITIONAL_DISABLE(VFPU_VEC);517if (js.HasUnknownPrefix()) {518DISABLE_UNKNOWN_PREFIX;519}520521// Pre-processing: Eliminate silly no-op VMOVs, common in Wipeout Pure522if (((op >> 16) & 0x1f) == 0 && _VS == _VD && js.HasNoPrefix()) {523return;524}525526// Must bail before we start mapping registers.527switch ((op >> 16) & 0x1f) {528case 0: // d[i] = s[i]; break; //vmov529case 1: // d[i] = fabsf(s[i]); break; //vabs530case 2: // d[i] = -s[i]; break; //vneg531case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq532break;533534default:535DISABLE;536break;537}538539VectorSize sz = GetVecSize(op);540int n = GetNumVectorElements(sz);541542MappedRegs r = NEONMapDirtyIn(op, sz, sz);543544ARMReg temp = MatchSize(Q0, r.vs);545546switch ((op >> 16) & 0x1f) {547case 0: // d[i] = s[i]; break; //vmov548// Probably for swizzle.549VMOV_neon(r.vd, r.vs);550break;551case 1: // d[i] = fabsf(s[i]); break; //vabs552VABS(F_32, r.vd, r.vs);553break;554case 2: // d[i] = -s[i]; break; //vneg555VNEG(F_32, r.vd, r.vs);556break;557558case 4: // if (s[i] < 0) d[i] = 0; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat0559if (IsD(r.vd)) {560VMOV_immf(D0, 0.0f);561VMOV_immf(D1, 1.0f);562VMAX(F_32, r.vd, r.vs, D0);563VMIN(F_32, r.vd, r.vd, D1);564} else {565VMOV_immf(Q0, 1.0f);566VMIN(F_32, r.vd, r.vs, Q0);567VMOV_immf(Q0, 0.0f);568VMAX(F_32, r.vd, r.vd, Q0);569}570break;571case 5: // if (s[i] < -1.0f) d[i] = -1.0f; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat1572if (IsD(r.vd)) {573VMOV_immf(D0, -1.0f);574VMOV_immf(D1, 1.0f);575VMAX(F_32, r.vd, r.vs, D0);576VMIN(F_32, r.vd, r.vd, D1);577} else {578VMOV_immf(Q0, 1.0f);579VMIN(F_32, r.vd, r.vs, Q0);580VMOV_immf(Q0, -1.0f);581VMAX(F_32, r.vd, r.vd, Q0);582}583break;584585case 16: // d[i] = 1.0f / s[i]; break; //vrcp586// Can just fallback to VFP and use VDIV.587DISABLE;588{589ARMReg temp2 = fpr.QAllocTemp(sz);590// Needs iterations on NEON. And two temps - which is a problem if vs == vd! Argh!591VRECPE(F_32, temp, r.vs);592VRECPS(temp2, r.vs, temp);593VMUL(F_32, temp2, temp2, temp);594VRECPS(temp2, r.vs, temp);595VMUL(F_32, temp2, temp2, temp);596}597// http://stackoverflow.com/questions/6759897/how-to-divide-in-neon-intrinsics-by-a-float-number598// reciprocal = vrecpeq_f32(b);599// reciprocal = vmulq_f32(vrecpsq_f32(b, reciprocal), reciprocal);600// reciprocal = vmulq_f32(vrecpsq_f32(b, reciprocal), reciprocal);601DISABLE;602break;603604case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq605DISABLE;606// Needs iterations on NEON607{608if (true) {609// Not-very-accurate estimate610VRSQRTE(F_32, r.vd, r.vs);611} else {612ARMReg temp2 = fpr.QAllocTemp(sz);613// TODO: It's likely that some games will require one or two Newton-Raphson614// iterations to refine the estimate.615VRSQRTE(F_32, temp, r.vs);616VRSQRTS(temp2, r.vs, temp);617VMUL(F_32, r.vd, temp2, temp);618//VRSQRTS(temp2, r.vs, temp);619// VMUL(F_32, r.vd, temp2, temp);620}621}622break;623case 18: // d[i] = sinf((float)M_PI_2 * s[i]); break; //vsin624DISABLE;625break;626case 19: // d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos627DISABLE;628break;629case 20: // d[i] = powf(2.0f, s[i]); break; //vexp2630DISABLE;631break;632case 21: // d[i] = logf(s[i])/log(2.0f); break; //vlog2633DISABLE;634break;635case 22: // d[i] = sqrtf(s[i]); break; //vsqrt636// Let's just defer to VFP for now. Better than calling the interpreter for sure.637VMOV_neon(MatchSize(Q0, r.vs), r.vs);638for (int i = 0; i < n; i++) {639VSQRT((ARMReg)(S0 + i), (ARMReg)(S0 + i));640}641VMOV_neon(MatchSize(Q0, r.vd), r.vd);642break;643case 23: // d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin644DISABLE;645break;646case 24: // d[i] = -1.0f / s[i]; break; // vnrcp647// Needs iterations on NEON. Just do the same as vrcp and negate.648DISABLE;649break;650case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin651DISABLE;652break;653case 28: // d[i] = 1.0f / expf(s[i] * (float)M_LOG2E); break; // vrexp2654DISABLE;655break;656default:657DISABLE;658break;659}660661NEONApplyPrefixD(r.vd);662663fpr.ReleaseSpillLocksAndDiscardTemps();664}665666void ArmJit::CompNEON_Mftv(MIPSOpcode op) {667CONDITIONAL_DISABLE(VFPU_XFER);668int imm = op & 0xFF;669MIPSGPReg rt = _RT;670switch ((op >> 21) & 0x1f) {671case 3: //mfv / mfvc672// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.673if (rt != 0) {674if (imm < 128) { //R(rt) = VI(imm);675ARMReg r = fpr.QMapReg(imm, V_Single, MAP_READ);676gpr.MapReg(rt, MAP_NOINIT | MAP_DIRTY);677// TODO: Gotta be a faster way678VMOV_neon(MatchSize(Q0, r), r);679VMOV(gpr.R(rt), S0);680} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc681// In case we have a saved prefix.682FlushPrefixV();683if (imm - 128 == VFPU_CTRL_CC) {684gpr.MapDirtyIn(rt, MIPS_REG_VFPUCC);685MOV(gpr.R(rt), gpr.R(MIPS_REG_VFPUCC));686} else {687gpr.MapReg(rt, MAP_NOINIT | MAP_DIRTY);688LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128));689}690} else {691//ERROR - maybe need to make this value too an "interlock" value?692ERROR_LOG(Log::CPU, "mfv - invalid register %i", imm);693}694}695break;696697case 7: // mtv698if (imm < 128) {699// TODO: It's pretty common that this is preceded by mfc1, that is, a value is being700// moved from the regular floating point registers. It would probably be faster to do701// the copy directly in the FPRs instead of going through the GPRs.702703ARMReg r = fpr.QMapReg(imm, V_Single, MAP_DIRTY | MAP_NOINIT);704if (gpr.IsMapped(rt)) {705VMOV(S0, gpr.R(rt));706VMOV_neon(r, MatchSize(Q0, r));707} else {708ADDI2R(R0, CTXREG, gpr.GetMipsRegOffset(rt), R1);709VLD1_lane(F_32, r, R0, 0, true);710}711} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc //currentMIPS->vfpuCtrl[imm - 128] = R(rt);712if (imm - 128 == VFPU_CTRL_CC) {713gpr.MapDirtyIn(MIPS_REG_VFPUCC, rt);714MOV(gpr.R(MIPS_REG_VFPUCC), rt);715} else {716gpr.MapReg(rt);717STR(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128));718}719720// TODO: Optimization if rt is Imm?721// Set these BEFORE disable!722if (imm - 128 == VFPU_CTRL_SPREFIX) {723js.prefixSFlag = JitState::PREFIX_UNKNOWN;724js.blockWrotePrefixes = true;725} else if (imm - 128 == VFPU_CTRL_TPREFIX) {726js.prefixTFlag = JitState::PREFIX_UNKNOWN;727js.blockWrotePrefixes = true;728} else if (imm - 128 == VFPU_CTRL_DPREFIX) {729js.prefixDFlag = JitState::PREFIX_UNKNOWN;730js.blockWrotePrefixes = true;731}732} else {733//ERROR734_dbg_assert_msg_(false,"mtv - invalid register");735}736break;737738default:739DISABLE;740}741742fpr.ReleaseSpillLocksAndDiscardTemps();743}744745void ArmJit::CompNEON_Vmfvc(MIPSOpcode op) {746DISABLE;747}748749void ArmJit::CompNEON_Vmtvc(MIPSOpcode op) {750CONDITIONAL_DISABLE(VFPU_XFER);751752int vs = _VS;753int imm = op & 0xFF;754if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {755ARMReg r = fpr.QMapReg(vs, V_Single, 0);756ADDI2R(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + (imm - 128) * 4, R1);757VST1_lane(F_32, r, R0, 0, true);758fpr.ReleaseSpillLocksAndDiscardTemps();759760if (imm - 128 == VFPU_CTRL_SPREFIX) {761js.prefixSFlag = JitState::PREFIX_UNKNOWN;762js.blockWrotePrefixes = true;763} else if (imm - 128 == VFPU_CTRL_TPREFIX) {764js.prefixTFlag = JitState::PREFIX_UNKNOWN;765js.blockWrotePrefixes = true;766} else if (imm - 128 == VFPU_CTRL_DPREFIX) {767js.prefixDFlag = JitState::PREFIX_UNKNOWN;768js.blockWrotePrefixes = true;769}770}771}772773void ArmJit::CompNEON_VMatrixInit(MIPSOpcode op) {774CONDITIONAL_DISABLE(VFPU_XFER);775776MatrixSize msz = GetMtxSize(op);777int n = GetMatrixSide(msz);778779ARMReg cols[4];780fpr.QMapMatrix(cols, _VD, msz, MAP_NOINIT | MAP_DIRTY);781782switch ((op >> 16) & 0xF) {783case 3: // vmidt784// There has to be a better way to synthesize: 1.0, 0.0, 0.0, 1.0 in a quad785VEOR(D0, D0, D0);786VMOV_immf(D1, 1.0f);787VTRN(F_32, D0, D1);788VREV64(I_32, D0, D0);789switch (msz) {790case M_2x2:791VMOV_neon(cols[0], D0);792VMOV_neon(cols[1], D1);793break;794case M_3x3:795VMOV_neon(D_0(cols[0]), D0);796VMOV_imm(I_8, D_1(cols[0]), VIMMxxxxxxxx, 0);797VMOV_neon(D_0(cols[1]), D1);798VMOV_imm(I_8, D_1(cols[1]), VIMMxxxxxxxx, 0);799VMOV_imm(I_8, D_0(cols[2]), VIMMxxxxxxxx, 0);800VMOV_neon(D_1(cols[2]), D0);801break;802case M_4x4:803VMOV_neon(D_0(cols[0]), D0);804VMOV_imm(I_8, D_1(cols[0]), VIMMxxxxxxxx, 0);805VMOV_neon(D_0(cols[1]), D1);806VMOV_imm(I_8, D_1(cols[1]), VIMMxxxxxxxx, 0);807VMOV_imm(I_8, D_0(cols[2]), VIMMxxxxxxxx, 0);808VMOV_neon(D_1(cols[2]), D0);809VMOV_imm(I_8, D_0(cols[3]), VIMMxxxxxxxx, 0);810VMOV_neon(D_1(cols[3]), D1);811812// NEONTranspose4x4(cols);813break;814default:815_assert_msg_(false, "Bad matrix size");816break;817}818break;819case 6: // vmzero820for (int i = 0; i < n; i++) {821VEOR(cols[i], cols[i], cols[i]);822}823break;824case 7: // vmone825for (int i = 0; i < n; i++) {826VMOV_immf(cols[i], 1.0f);827}828break;829}830831fpr.ReleaseSpillLocksAndDiscardTemps();832}833834void ArmJit::CompNEON_Vmmov(MIPSOpcode op) {835CONDITIONAL_DISABLE(VFPU_MTX_VMMOV);836if (_VS == _VD) {837// A lot of these no-op matrix moves in Wipeout... Just drop the instruction entirely.838return;839}840841MatrixSize msz = GetMtxSize(op);842843MatrixOverlapType overlap = GetMatrixOverlap(_VD, _VS, msz);844if (overlap != OVERLAP_NONE) {845// Too complicated to bother handling in the JIT.846// TODO: Special case for in-place (and other) transpose, etc.847DISABLE;848}849850ARMReg s_cols[4], d_cols[4];851fpr.QMapMatrix(s_cols, _VS, msz, 0);852fpr.QMapMatrix(d_cols, _VD, msz, MAP_DIRTY | MAP_NOINIT);853854int n = GetMatrixSide(msz);855for (int i = 0; i < n; i++) {856VMOV_neon(d_cols[i], s_cols[i]);857}858859fpr.ReleaseSpillLocksAndDiscardTemps();860}861862void ArmJit::CompNEON_Vmmul(MIPSOpcode op) {863CONDITIONAL_DISABLE(VFPU_MTX_VMMUL);864865MatrixSize msz = GetMtxSize(op);866int n = GetMatrixSide(msz);867868bool overlap = GetMatrixOverlap(_VD, _VS, msz) || GetMatrixOverlap(_VD, _VT, msz);869if (overlap) {870// Later. Fortunately, the VFPU also seems to prohibit overlap for matrix mul.871INFO_LOG(Log::JIT, "Matrix overlap, ignoring.");872DISABLE;873}874875// Having problems with 2x2s for some reason.876if (msz == M_2x2) {877DISABLE;878}879880ARMReg s_cols[4], t_cols[4], d_cols[4];881882// For some reason, vmmul is encoded with the first matrix (S) transposed from the real meaning.883fpr.QMapMatrix(t_cols, _VT, msz, MAP_FORCE_LOW); // Need to see if we can avoid having to force it low in some sane way. Will need crazy prediction logic for loads otherwise.884fpr.QMapMatrix(s_cols, Xpose(_VS), msz, MAP_PREFER_HIGH);885fpr.QMapMatrix(d_cols, _VD, msz, MAP_PREFER_HIGH | MAP_NOINIT | MAP_DIRTY);886887// TODO: Getting there but still getting wrong results.888for (int i = 0; i < n; i++) {889for (int j = 0; j < n; j++) {890if (i == 0) {891VMUL_scalar(F_32, d_cols[j], s_cols[i], XScalar(t_cols[j], i));892} else {893VMLA_scalar(F_32, d_cols[j], s_cols[i], XScalar(t_cols[j], i));894}895}896}897898fpr.ReleaseSpillLocksAndDiscardTemps();899}900901void ArmJit::CompNEON_Vmscl(MIPSOpcode op) {902CONDITIONAL_DISABLE(VFPU_MTX_VMSCL);903904MatrixSize msz = GetMtxSize(op);905906bool overlap = GetMatrixOverlap(_VD, _VS, msz) != OVERLAP_NONE;907if (overlap) {908DISABLE;909}910911int n = GetMatrixSide(msz);912913ARMReg s_cols[4], t, d_cols[4];914fpr.QMapMatrix(s_cols, _VS, msz, 0);915fpr.QMapMatrix(d_cols, _VD, msz, MAP_NOINIT | MAP_DIRTY);916917t = fpr.QMapReg(_VT, V_Single, 0);918VMOV_neon(D0, t);919for (int i = 0; i < n; i++) {920VMUL_scalar(F_32, d_cols[i], s_cols[i], DScalar(D0, 0));921}922923fpr.ReleaseSpillLocksAndDiscardTemps();924}925926void ArmJit::CompNEON_Vtfm(MIPSOpcode op) {927CONDITIONAL_DISABLE(VFPU_MTX_VTFM);928if (js.HasUnknownPrefix()) {929DISABLE;930}931932if (_VT == _VD) {933DISABLE;934}935936VectorSize sz = GetVecSize(op);937MatrixSize msz = GetMtxSize(op);938int n = GetNumVectorElements(sz);939int ins = (op >> 23) & 7;940941bool homogenous = false;942if (n == ins) {943n++;944sz = (VectorSize)((int)(sz)+1);945msz = (MatrixSize)((int)(msz)+1);946homogenous = true;947}948// Otherwise, n should already be ins + 1.949else if (n != ins + 1) {950DISABLE;951}952953ARMReg s_cols[4], t, d;954t = fpr.QMapReg(_VT, sz, MAP_FORCE_LOW);955fpr.QMapMatrix(s_cols, Xpose(_VS), msz, MAP_PREFER_HIGH);956d = fpr.QMapReg(_VD, sz, MAP_DIRTY | MAP_NOINIT | MAP_PREFER_HIGH);957958VMUL_scalar(F_32, d, s_cols[0], XScalar(t, 0));959for (int i = 1; i < n; i++) {960if (homogenous && i == n - 1) {961VADD(F_32, d, d, s_cols[i]);962} else {963VMLA_scalar(F_32, d, s_cols[i], XScalar(t, i));964}965}966967// VTFM does not have prefix support.968969fpr.ReleaseSpillLocksAndDiscardTemps();970}971972void ArmJit::CompNEON_VCrs(MIPSOpcode op) {973DISABLE;974}975976void ArmJit::CompNEON_VDet(MIPSOpcode op) {977DISABLE;978}979980void ArmJit::CompNEON_Vi2x(MIPSOpcode op) {981DISABLE;982}983984void ArmJit::CompNEON_Vx2i(MIPSOpcode op) {985DISABLE;986}987988void ArmJit::CompNEON_Vf2i(MIPSOpcode op) {989DISABLE;990}991992void ArmJit::CompNEON_Vi2f(MIPSOpcode op) {993CONDITIONAL_DISABLE(VFPU_VEC);994if (js.HasUnknownPrefix()) {995DISABLE;996}997998DISABLE;9991000VectorSize sz = GetVecSize(op);1001int n = GetNumVectorElements(sz);10021003int imm = (op >> 16) & 0x1f;1004const float mult = 1.0f / (float)(1UL << imm);10051006MappedRegs regs = NEONMapDirtyIn(op, sz, sz);10071008MOVI2F_neon(MatchSize(Q0, regs.vd), mult, R0);10091010VCVT(F_32, regs.vd, regs.vs);1011VMUL(F_32, regs.vd, regs.vd, Q0);10121013NEONApplyPrefixD(regs.vd);10141015fpr.ReleaseSpillLocksAndDiscardTemps();1016}10171018void ArmJit::CompNEON_Vh2f(MIPSOpcode op) {1019CONDITIONAL_DISABLE(VFPU_VEC);1020if (!cpu_info.bHalf) {1021// No hardware support for half-to-float, fallback to interpreter1022// TODO: Translate the fast SSE solution to standard integer/VFP stuff1023// for the weaker CPUs.1024DISABLE;1025}10261027VectorSize sz = GetVecSize(op);10281029VectorSize outsize = V_Pair;1030switch (sz) {1031case V_Single:1032outsize = V_Pair;1033break;1034case V_Pair:1035outsize = V_Quad;1036break;1037default:1038ERROR_LOG(Log::JIT, "Vh2f: Must be pair or quad");1039break;1040}10411042ARMReg vs = NEONMapPrefixS(_VS, sz, 0);1043// TODO: MAP_NOINIT if they're definitely not overlapping.1044DestARMReg vd = NEONMapPrefixD(_VD, outsize, MAP_DIRTY);10451046VCVTF32F16(vd.rd, vs);10471048NEONApplyPrefixD(vd);1049fpr.ReleaseSpillLocksAndDiscardTemps();1050}10511052void ArmJit::CompNEON_Vcst(MIPSOpcode op) {1053CONDITIONAL_DISABLE(VFPU_XFER);1054if (js.HasUnknownPrefix()) {1055DISABLE_UNKNOWN_PREFIX;1056}10571058int conNum = (op >> 16) & 0x1f;10591060VectorSize sz = GetVecSize(op);1061int n = GetNumVectorElements(sz);1062DestARMReg vd = NEONMapPrefixD(_VD, sz, MAP_DIRTY | MAP_NOINIT);1063gpr.SetRegImm(R0, (u32)(void *)&cst_constants[conNum]);1064VLD1_all_lanes(F_32, vd, R0, true);1065NEONApplyPrefixD(vd); // TODO: Could bake this into the constant we load.10661067fpr.ReleaseSpillLocksAndDiscardTemps();1068}10691070void ArmJit::CompNEON_Vhoriz(MIPSOpcode op) {1071CONDITIONAL_DISABLE(VFPU_VEC);1072if (js.HasUnknownPrefix()) {1073DISABLE_UNKNOWN_PREFIX;1074}1075VectorSize sz = GetVecSize(op);1076// Do any games use these a noticeable amount?1077switch ((op >> 16) & 31) {1078case 6: // vfad1079{1080VMOV_neon(F_32, D1, 0.0f);1081MappedRegs r = NEONMapDirtyIn(op, V_Single, sz);1082switch (sz) {1083case V_Pair:1084VPADD(F_32, r.vd, r.vs, r.vs);1085break;1086case V_Triple:1087VPADD(F_32, D0, D_0(r.vs), D_0(r.vs));1088VADD(F_32, r.vd, D0, D_1(r.vs));1089break;1090case V_Quad:1091VADD(F_32, D0, D_0(r.vs), D_1(r.vs));1092VPADD(F_32, r.vd, D0, D0);1093break;1094default:1095;1096}1097// This forces the sign of -0.000 to +0.000.1098VADD(F_32, r.vd, r.vd, D1);1099break;1100}11011102case 7: // vavg1103DISABLE;1104break;1105}1106fpr.ReleaseSpillLocksAndDiscardTemps();1107}11081109void ArmJit::CompNEON_VRot(MIPSOpcode op) {1110CONDITIONAL_DISABLE(VFPU_VEC);11111112if (js.HasUnknownPrefix()) {1113DISABLE_UNKNOWN_PREFIX;1114}11151116DISABLE;11171118int vd = _VD;1119int vs = _VS;11201121VectorSize sz = GetVecSize(op);1122int n = GetNumVectorElements(sz);11231124// ...1125fpr.ReleaseSpillLocksAndDiscardTemps();1126}11271128void ArmJit::CompNEON_VIdt(MIPSOpcode op) {1129CONDITIONAL_DISABLE(VFPU_XFER);1130if (js.HasUnknownPrefix()) {1131DISABLE_UNKNOWN_PREFIX;1132}11331134VectorSize sz = GetVecSize(op);1135DestARMReg vd = NEONMapPrefixD(_VD, sz, MAP_NOINIT | MAP_DIRTY);1136switch (sz) {1137case V_Pair:1138VMOV_immf(vd, 1.0f);1139if ((_VD & 1) == 0) {1140// Load with 1.0, 0.01141VMOV_imm(I_64, D0, VIMMbits2bytes, 0x0F);1142VAND(vd, vd, D0);1143} else {1144VMOV_imm(I_64, D0, VIMMbits2bytes, 0xF0);1145VAND(vd, vd, D0);1146}1147break;1148case V_Triple:1149case V_Quad:1150{1151// TODO: This can be optimized.1152VEOR(vd, vd, vd);1153ARMReg dest = (_VD & 2) ? D_1(vd) : D_0(vd);1154VMOV_immf(dest, 1.0f);1155if ((_VD & 1) == 0) {1156// Load with 1.0, 0.01157VMOV_imm(I_64, D0, VIMMbits2bytes, 0x0F);1158VAND(dest, dest, D0);1159} else {1160VMOV_imm(I_64, D0, VIMMbits2bytes, 0xF0);1161VAND(dest, dest, D0);1162}1163}1164break;1165default:1166_dbg_assert_msg_(false,"Bad vidt instruction");1167break;1168}11691170NEONApplyPrefixD(vd);1171fpr.ReleaseSpillLocksAndDiscardTemps();1172}11731174void ArmJit::CompNEON_Vcmp(MIPSOpcode op) {1175CONDITIONAL_DISABLE(VFPU_COMP);1176if (js.HasUnknownPrefix())1177DISABLE;11781179// Not a chance that this works on the first try :P1180DISABLE;11811182VectorSize sz = GetVecSize(op);1183int n = GetNumVectorElements(sz);11841185VCondition cond = (VCondition)(op & 0xF);11861187MappedRegs regs = NEONMapInIn(op, sz, sz);11881189ARMReg vs = regs.vs, vt = regs.vt;1190ARMReg res = fpr.QAllocTemp(sz);11911192// Some, we just fall back to the interpreter.1193// ES is just really equivalent to (value & 0x7F800000) == 0x7F800000.1194switch (cond) {1195case VC_EI: // c = my_isinf(s[i]); break;1196case VC_NI: // c = !my_isinf(s[i]); break;1197DISABLE;1198case VC_ES: // c = my_isnan(s[i]) || my_isinf(s[i]); break; // Tekken Dark Resurrection1199case VC_NS: // c = !my_isnan(s[i]) && !my_isinf(s[i]); break;1200case VC_EN: // c = my_isnan(s[i]); break;1201case VC_NN: // c = !my_isnan(s[i]); break;1202// if (_VS != _VT)1203DISABLE;1204break;12051206case VC_EZ:1207case VC_NZ:1208VMOV_immf(Q0, 0.0f);1209break;1210default:1211;1212}12131214int affected_bits = (1 << 4) | (1 << 5); // 4 and 51215for (int i = 0; i < n; i++) {1216affected_bits |= 1 << i;1217}12181219// Preload the pointer to our magic mask1220static const u32 collectorBits[4] = { 1, 2, 4, 8 };1221MOVP2R(R1, &collectorBits);12221223// Do the compare1224MOVI2R(R0, 0);1225CCFlags flag = CC_AL;12261227bool oneIsFalse = false;1228switch (cond) {1229case VC_FL: // c = 0;1230break;12311232case VC_TR: // c = 11233MOVI2R(R0, affected_bits);1234break;12351236case VC_ES: // c = my_isnan(s[i]) || my_isinf(s[i]); break; // Tekken Dark Resurrection1237case VC_NS: // c = !(my_isnan(s[i]) || my_isinf(s[i])); break;1238DISABLE; // TODO: these shouldn't be that hard1239break;12401241case VC_EN: // c = my_isnan(s[i]); break; // Tekken 61242case VC_NN: // c = !my_isnan(s[i]); break;1243DISABLE; // TODO: these shouldn't be that hard1244break;12451246case VC_EQ: // c = s[i] == t[i]1247VCEQ(F_32, res, vs, vt);1248break;12491250case VC_LT: // c = s[i] < t[i]1251VCLT(F_32, res, vs, vt);1252break;12531254case VC_LE: // c = s[i] <= t[i];1255VCLE(F_32, res, vs, vt);1256break;12571258case VC_NE: // c = s[i] != t[i]1259VCEQ(F_32, res, vs, vt);1260oneIsFalse = true;1261break;12621263case VC_GE: // c = s[i] >= t[i]1264VCGE(F_32, res, vs, vt);1265break;12661267case VC_GT: // c = s[i] > t[i]1268VCGT(F_32, res, vs, vt);1269break;12701271case VC_EZ: // c = s[i] == 0.0f || s[i] == -0.0f1272VCEQ(F_32, res, vs);1273break;12741275case VC_NZ: // c = s[i] != 01276VCEQ(F_32, res, vs);1277oneIsFalse = true;1278break;12791280default:1281DISABLE;1282}1283if (oneIsFalse) {1284VMVN(res, res);1285}1286// Somehow collect the bits into a mask.12871288// Collect the bits. Where's my PMOVMSKB? :(1289VLD1(I_32, Q0, R1, n < 2 ? 1 : 2);1290VAND(Q0, Q0, res);1291VPADD(I_32, Q0, Q0, Q0);1292VPADD(I_32, D0, D0, D0);1293// OK, bits now in S0.1294VMOV(R0, S0);1295// Zap irrelevant bits (V_Single, V_Triple)1296AND(R0, R0, affected_bits);12971298// TODO: Now, how in the world do we generate the component OR and AND bits without burning tens of ALU instructions?? Lookup-table?12991300gpr.MapReg(MIPS_REG_VFPUCC, MAP_DIRTY);1301BIC(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), affected_bits);1302ORR(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), R0);1303}13041305void ArmJit::CompNEON_Vcmov(MIPSOpcode op) {1306CONDITIONAL_DISABLE(VFPU_COMP);1307if (js.HasUnknownPrefix()) {1308DISABLE;1309}13101311DISABLE;13121313VectorSize sz = GetVecSize(op);1314int n = GetNumVectorElements(sz);13151316ARMReg vs = NEONMapPrefixS(_VS, sz, 0);1317DestARMReg vd = NEONMapPrefixD(_VD, sz, MAP_DIRTY);1318int tf = (op >> 19) & 1;1319int imm3 = (op >> 16) & 7;13201321if (imm3 < 6) {1322// Test one bit of CC. This bit decides whether none or all subregisters are copied.1323gpr.MapReg(MIPS_REG_VFPUCC);1324TST(gpr.R(MIPS_REG_VFPUCC), 1 << imm3);1325FixupBranch skip = B_CC(CC_NEQ);1326VMOV_neon(vd, vs);1327SetJumpTarget(skip);1328} else {1329// Look at the bottom four bits of CC to individually decide if the subregisters should be copied.1330// This is the nasty one! Need to expand those bits into a full NEON register somehow.1331DISABLE;1332/*1333gpr.MapReg(MIPS_REG_VFPUCC);1334for (int i = 0; i < n; i++) {1335TST(gpr.R(MIPS_REG_VFPUCC), 1 << i);1336SetCC(tf ? CC_EQ : CC_NEQ);1337VMOV(fpr.V(dregs[i]), fpr.V(sregs[i]));1338SetCC(CC_AL);1339}1340*/1341}13421343NEONApplyPrefixD(vd);13441345fpr.ReleaseSpillLocksAndDiscardTemps();1346}13471348void ArmJit::CompNEON_Viim(MIPSOpcode op) {1349CONDITIONAL_DISABLE(VFPU_XFER);1350if (js.HasUnknownPrefix()) {1351DISABLE;1352}13531354DestARMReg vt = NEONMapPrefixD(_VT, V_Single, MAP_NOINIT | MAP_DIRTY);13551356s32 imm = SignExtend16ToS32(op);1357// TODO: Optimize for low registers.1358MOVI2F(S0, (float)imm, R0);1359VMOV_neon(vt.rd, D0);13601361NEONApplyPrefixD(vt);1362fpr.ReleaseSpillLocksAndDiscardTemps();1363}13641365void ArmJit::CompNEON_Vfim(MIPSOpcode op) {1366CONDITIONAL_DISABLE(VFPU_XFER);1367if (js.HasUnknownPrefix()) {1368DISABLE;1369}13701371DestARMReg vt = NEONMapPrefixD(_VT, V_Single, MAP_NOINIT | MAP_DIRTY);13721373FP16 half;1374half.u = op & 0xFFFF;1375FP32 fval = half_to_float_fast5(half);1376// TODO: Optimize for low registers.1377MOVI2F(S0, (float)fval.f, R0);1378VMOV_neon(vt.rd, D0);13791380NEONApplyPrefixD(vt);1381fpr.ReleaseSpillLocksAndDiscardTemps();1382}13831384// https://code.google.com/p/bullet/source/browse/branches/PhysicsEffects/include/vecmath/neon/vectormath_neon_assembly_implementations.S?r=24881385void ArmJit::CompNEON_VCrossQuat(MIPSOpcode op) {1386// This op does not support prefixes anyway.1387CONDITIONAL_DISABLE(VFPU_VEC);1388if (js.HasUnknownPrefix()) {1389DISABLE_UNKNOWN_PREFIX;1390}13911392VectorSize sz = GetVecSize(op);1393if (sz != V_Triple) {1394// Quaternion product. Bleh.1395DISABLE;1396}13971398MappedRegs r = NEONMapDirtyInIn(op, sz, sz, sz, false);13991400ARMReg t1 = Q0;1401ARMReg t2 = fpr.QAllocTemp(V_Triple);14021403// There has to be a faster way to do this. This is not really any better than1404// scalar.14051406// d18, d19 (q9) = t1 = r.vt1407// d16, d17 (q8) = t2 = r.vs1408// d20, d21 (q10) = t1409VMOV_neon(t1, r.vs);1410VMOV_neon(t2, r.vt);1411VTRN(F_32, D_0(t2), D_1(t2)); // vtrn.32 d18,d19 @ q9 = <x2,z2,y2,w2> = d18,d191412VREV64(F_32, D_0(t1), D_0(t1)); // vrev64.32 d16,d16 @ q8 = <y1,x1,z1,w1> = d16,d171413VREV64(F_32, D_0(t2), D_0(t2)); // vrev64.32 d18,d18 @ q9 = <z2,x2,y2,w2> = d18,d191414VTRN(F_32, D_0(t1), D_1(t1)); // vtrn.32 d16,d17 @ q8 = <y1,z1,x1,w1> = d16,d171415// perform first half of cross product using rearranged inputs1416VMUL(F_32, r.vd, t1, t2); // vmul.f32 q10, q8, q9 @ q10 = <y1*z2,z1*x2,x1*y2,w1*w2>1417// @ rearrange inputs again1418VTRN(F_32, D_0(t2), D_1(t2)); // vtrn.32 d18,d19 @ q9 = <z2,y2,x2,w2> = d18,d191419VREV64(F_32, D_0(t1), D_0(t1)); // vrev64.32 d16,d16 @ q8 = <z1,y1,x1,w1> = d16,d171420VREV64(F_32, D_0(t2), D_0(t2)); // vrev64.32 d18,d18 @ q9 = <y2,z2,x2,w2> = d18,d191421VTRN(F_32, D_0(t1), D_1(t1)); // vtrn.32 d16,d17 @ q8 = <z1,x1,y1,w1> = d16,d171422// @ perform last half of cross product using rearranged inputs1423VMLS(F_32, r.vd, t1, t2); // vmls.f32 q10, q8, q9 @ q10 = <y1*z2-y2*z1,z1*x2-z2*x1,x1*y2-x2*y1,w1*w2-w2*w1>14241425fpr.ReleaseSpillLocksAndDiscardTemps();1426}14271428void ArmJit::CompNEON_Vsgn(MIPSOpcode op) {1429DISABLE;14301431// This will be a bunch of bit magic.1432}14331434void ArmJit::CompNEON_Vocp(MIPSOpcode op) {1435CONDITIONAL_DISABLE(VFPU_VEC);1436if (js.HasUnknownPrefix()) {1437DISABLE;1438}14391440// TODO: Handle T prefix. Right now it uses 1.0f always.14411442// This is a hack that modifies prefixes. We eat them later, so just overwrite.1443// S prefix forces the negate flags.1444js.prefixS |= 0x000F0000;1445// T prefix forces constants on and regnum to 1.1446// That means negate still works, and abs activates a different constant.1447js.prefixT = (js.prefixT & ~0x000000FF) | 0x00000055 | 0x0000F000;14481449VectorSize sz = GetVecSize(op);1450int n = GetNumVectorElements(sz);14511452MappedRegs regs = NEONMapDirtyIn(op, sz, sz);1453MOVI2F_neon(Q0, 1.0f, R0);1454VADD(F_32, regs.vd, Q0, regs.vs);1455NEONApplyPrefixD(regs.vd);14561457fpr.ReleaseSpillLocksAndDiscardTemps();1458}14591460void ArmJit::CompNEON_ColorConv(MIPSOpcode op) {1461DISABLE;1462}14631464void ArmJit::CompNEON_Vbfy(MIPSOpcode op) {1465DISABLE;1466}14671468}1469// namespace MIPSComp14701471#endif // PPSSPP_ARCH(ARM)147214731474