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Path: blob/master/Core/MIPS/ARM/ArmRegCache.cpp
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// Copyright (c) 2012- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "ppsspp_config.h"18#if PPSSPP_ARCH(ARM)1920#include "Core/MemMap.h"21#include "Core/MIPS/ARM/ArmRegCache.h"22#include "Core/MIPS/ARM/ArmJit.h"23#include "Core/MIPS/MIPSAnalyst.h"24#include "Core/Reporting.h"25#include "Common/ArmEmitter.h"2627#ifndef offsetof28#include "stddef.h"29#endif3031using namespace ArmGen;32using namespace ArmJitConstants;3334ArmRegCache::ArmRegCache(MIPSState *mipsState, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mipsState), js_(js), jo_(jo) {35}3637void ArmRegCache::Init(ARMXEmitter *emitter) {38emit_ = emitter;39}4041void ArmRegCache::Start(MIPSAnalyst::AnalysisResults &stats) {42for (int i = 0; i < NUM_ARMREG; i++) {43ar[i].mipsReg = MIPS_REG_INVALID;44ar[i].isDirty = false;45}46for (int i = 0; i < NUM_MIPSREG; i++) {47mr[i].loc = ML_MEM;48mr[i].reg = INVALID_REG;49mr[i].imm = -1;50mr[i].spillLock = false;51}52}5354const ARMReg *ArmRegCache::GetMIPSAllocationOrder(int &count) {55// Note that R0 is reserved as scratch for now.56// R12 is also potentially usable.57// R4-R7 are registers we could use for static allocation or downcount.58// R8 is used to preserve flags in nasty branches.59// R9 and upwards are reserved for jit basics.60// R14 (LR) is used as a scratch reg (overwritten on calls/return.)61if (jo_->downcountInRegister) {62static const ARMReg allocationOrder[] = {63R1, R2, R3, R4, R5, R6, R12,64};65count = sizeof(allocationOrder) / sizeof(const int);66return allocationOrder;67} else {68static const ARMReg allocationOrder2[] = {69R1, R2, R3, R4, R5, R6, R7, R12,70};71count = sizeof(allocationOrder2) / sizeof(const int);72return allocationOrder2;73}74}7576void ArmRegCache::FlushBeforeCall() {77// R4-R11 are preserved. Others need flushing.78FlushArmReg(R1);79FlushArmReg(R2);80FlushArmReg(R3);81FlushArmReg(R12);82}8384ARMReg ArmRegCache::MapRegAsPointer(MIPSGPReg mipsReg) { // read-only, non-dirty.85// If already mapped as a pointer, bail.86if (mr[mipsReg].loc == ML_ARMREG_AS_PTR) {87return mr[mipsReg].reg;88}89// First, make sure the register is already mapped.90MapReg(mipsReg, 0);91// If it's dirty, flush it.92ARMReg armReg = mr[mipsReg].reg;93if (ar[armReg].isDirty) {94emit_->STR(armReg, CTXREG, GetMipsRegOffset(ar[armReg].mipsReg));95}96// Convert to a pointer by adding the base and clearing off the top bits.97// If SP, we can probably avoid the top bit clear, let's play with that later.98emit_->BIC(armReg, armReg, Operand2(0xC0, 4)); // &= 0x3FFFFFFF99emit_->ADD(armReg, MEMBASEREG, armReg);100ar[armReg].isDirty = false;101ar[armReg].mipsReg = mipsReg;102mr[mipsReg].loc = ML_ARMREG_AS_PTR;103return armReg;104}105106bool ArmRegCache::IsMappedAsPointer(MIPSGPReg mipsReg) {107return mr[mipsReg].loc == ML_ARMREG_AS_PTR;108}109110bool ArmRegCache::IsMapped(MIPSGPReg mipsReg) {111return mr[mipsReg].loc == ML_ARMREG;112}113114void ArmRegCache::SetRegImm(ARMReg reg, u32 imm) {115// If we can do it with a simple Operand2, let's do that.116Operand2 op2;117bool inverse;118if (TryMakeOperand2_AllowInverse(imm, op2, &inverse)) {119if (!inverse)120emit_->MOV(reg, op2);121else122emit_->MVN(reg, op2);123return;124}125126// Okay, so it's a bit more complex. Let's see if we have any useful regs with imm values.127for (int i = 0; i < NUM_MIPSREG; i++) {128const auto &mreg = mr[i];129if (mreg.loc != ML_ARMREG_IMM)130continue;131132if (mreg.imm - imm < 256) {133emit_->SUB(reg, mreg.reg, mreg.imm - imm);134return;135}136if (imm - mreg.imm < 256) {137emit_->ADD(reg, mreg.reg, imm - mreg.imm);138return;139}140// This could be common when using an address.141if ((mreg.imm & 0x3FFFFFFF) == imm) {142emit_->BIC(reg, mreg.reg, Operand2(0xC0, 4)); // &= 0x3FFFFFFF143return;144}145// TODO: All sorts of things are possible here, shifted adds, ands/ors, etc.146}147148// No luck. Let's go with a regular load.149emit_->MOVI2R(reg, imm);150}151152void ArmRegCache::MapRegTo(ARMReg reg, MIPSGPReg mipsReg, int mapFlags) {153ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;154if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {155if (mipsReg == MIPS_REG_ZERO) {156// If we get a request to load the zero register, at least we won't spend157// time on a memory access...158// TODO: EOR?159emit_->MOV(reg, 0);160161// This way, if we SetImm() it, we'll keep it.162mr[mipsReg].loc = ML_ARMREG_IMM;163mr[mipsReg].imm = 0;164} else {165switch (mr[mipsReg].loc) {166case ML_MEM:167emit_->LDR(reg, CTXREG, GetMipsRegOffset(mipsReg));168mr[mipsReg].loc = ML_ARMREG;169break;170case ML_IMM:171SetRegImm(reg, mr[mipsReg].imm);172ar[reg].isDirty = true; // IMM is always dirty.173174// If we are mapping dirty, it means we're gonna overwrite.175// So the imm value is no longer valid.176if (mapFlags & MAP_DIRTY)177mr[mipsReg].loc = ML_ARMREG;178else179mr[mipsReg].loc = ML_ARMREG_IMM;180break;181default:182mr[mipsReg].loc = ML_ARMREG;183break;184}185}186} else {187mr[mipsReg].loc = ML_ARMREG;188}189ar[reg].mipsReg = mipsReg;190mr[mipsReg].reg = reg;191}192193ARMReg ArmRegCache::FindBestToSpill(bool unusedOnly, bool *clobbered) {194int allocCount;195const ARMReg *allocOrder = GetMIPSAllocationOrder(allocCount);196197static const int UNUSED_LOOKAHEAD_OPS = 30;198199*clobbered = false;200for (int i = 0; i < allocCount; i++) {201ARMReg reg = allocOrder[i];202if (ar[reg].mipsReg != MIPS_REG_INVALID && mr[ar[reg].mipsReg].spillLock)203continue;204205// Awesome, a clobbered reg. Let's use it.206if (MIPSAnalyst::IsRegisterClobbered(ar[reg].mipsReg, compilerPC_, UNUSED_LOOKAHEAD_OPS)) {207*clobbered = true;208return reg;209}210211// Not awesome. A used reg. Let's try to avoid spilling.212if (unusedOnly && MIPSAnalyst::IsRegisterUsed(ar[reg].mipsReg, compilerPC_, UNUSED_LOOKAHEAD_OPS)) {213continue;214}215216return reg;217}218219return INVALID_REG;220}221222// TODO: Somewhat smarter spilling - currently simply spills the first available, should do223// round robin or FIFO or something.224ARMReg ArmRegCache::MapReg(MIPSGPReg mipsReg, int mapFlags) {225// Let's see if it's already mapped. If so we just need to update the dirty flag.226// We don't need to check for ML_NOINIT because we assume that anyone who maps227// with that flag immediately writes a "known" value to the register.228if (mr[mipsReg].loc == ML_ARMREG || mr[mipsReg].loc == ML_ARMREG_IMM) {229ARMReg armReg = mr[mipsReg].reg;230if (ar[armReg].mipsReg != mipsReg) {231ERROR_LOG_REPORT(Log::JIT, "Register mapping out of sync! %i", mipsReg);232}233if (mapFlags & MAP_DIRTY) {234// Mapping dirty means the old imm value is invalid.235mr[mipsReg].loc = ML_ARMREG;236ar[armReg].isDirty = true;237}238return (ARMReg)mr[mipsReg].reg;239} else if (mr[mipsReg].loc == ML_ARMREG_AS_PTR) {240// Was mapped as pointer, now we want it mapped as a value, presumably to241// add or subtract stuff to it. Later we could allow such things but for now242// let's just convert back to a register value by reloading from the backing storage.243ARMReg armReg = mr[mipsReg].reg;244if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {245emit_->LDR(armReg, CTXREG, GetMipsRegOffset(mipsReg));246}247mr[mipsReg].loc = ML_ARMREG;248if (mapFlags & MAP_DIRTY) {249ar[armReg].isDirty = true;250}251return (ARMReg)mr[mipsReg].reg;252}253254// Okay, not mapped, so we need to allocate an ARM register.255256int allocCount;257const ARMReg *allocOrder = GetMIPSAllocationOrder(allocCount);258259ARMReg desiredReg = INVALID_REG;260// Try to "statically" allocate the first 6 regs after v0.261int desiredOrder = allocCount - (6 - (mipsReg - (int)MIPS_REG_V0));262if (desiredOrder >= 0 && desiredOrder < allocCount)263desiredReg = allocOrder[desiredOrder];264265if (desiredReg != INVALID_REG) {266if (ar[desiredReg].mipsReg == MIPS_REG_INVALID) {267// With this placement, we may be able to optimize flush.268MapRegTo(desiredReg, mipsReg, mapFlags);269return desiredReg;270}271}272273allocate:274for (int i = 0; i < allocCount; i++) {275ARMReg reg = allocOrder[i];276277if (ar[reg].mipsReg == MIPS_REG_INVALID) {278// That means it's free. Grab it, and load the value into it (if requested).279MapRegTo(reg, mipsReg, mapFlags);280return reg;281}282}283284// Still nothing. Let's spill a reg and goto 10.285// TODO: Use age or something to choose which register to spill?286// TODO: Spill dirty regs first? or opposite?287bool clobbered;288ARMReg bestToSpill = FindBestToSpill(true, &clobbered);289if (bestToSpill == INVALID_REG) {290bestToSpill = FindBestToSpill(false, &clobbered);291}292293if (bestToSpill != INVALID_REG) {294// ERROR_LOG(Log::JIT, "Out of registers at PC %08x - spills register %i.", mips_->pc, bestToSpill);295// TODO: Broken somehow in Dante's Inferno, but most games work. Bad flags in MIPSTables somewhere?296if (clobbered) {297DiscardR(ar[bestToSpill].mipsReg);298} else {299FlushArmReg(bestToSpill);300}301goto allocate;302}303304// Uh oh, we have all of them spilllocked....305ERROR_LOG_REPORT(Log::JIT, "Out of spillable registers at PC %08x!!!", mips_->pc);306return INVALID_REG;307}308309void ArmRegCache::MapInIn(MIPSGPReg rd, MIPSGPReg rs) {310SpillLock(rd, rs);311MapReg(rd);312MapReg(rs);313ReleaseSpillLocks();314}315316void ArmRegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) {317SpillLock(rd, rs);318bool load = !avoidLoad || rd == rs;319MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);320MapReg(rs);321ReleaseSpillLocks();322}323324void ArmRegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {325SpillLock(rd, rs, rt);326bool load = !avoidLoad || (rd == rs || rd == rt);327MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);328MapReg(rt);329MapReg(rs);330ReleaseSpillLocks();331}332333void ArmRegCache::MapDirtyDirtyIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, bool avoidLoad) {334SpillLock(rd1, rd2, rs);335bool load1 = !avoidLoad || rd1 == rs;336bool load2 = !avoidLoad || rd2 == rs;337MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);338MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);339MapReg(rs);340ReleaseSpillLocks();341}342343void ArmRegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {344SpillLock(rd1, rd2, rs, rt);345bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt);346bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt);347MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);348MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);349MapReg(rt);350MapReg(rs);351ReleaseSpillLocks();352}353354void ArmRegCache::FlushArmReg(ARMReg r) {355if (ar[r].mipsReg == MIPS_REG_INVALID) {356// Nothing to do, reg not mapped.357if (ar[r].isDirty) {358ERROR_LOG_REPORT(Log::JIT, "Dirty but no mipsreg?");359}360return;361}362if (ar[r].mipsReg != MIPS_REG_INVALID) {363auto &mreg = mr[ar[r].mipsReg];364if (mreg.loc == ML_ARMREG_IMM || ar[r].mipsReg == MIPS_REG_ZERO) {365// We know its immedate value, no need to STR now.366mreg.loc = ML_IMM;367mreg.reg = INVALID_REG;368} else {369if (ar[r].isDirty && mreg.loc == ML_ARMREG)370emit_->STR(r, CTXREG, GetMipsRegOffset(ar[r].mipsReg));371mreg.loc = ML_MEM;372mreg.reg = INVALID_REG;373mreg.imm = 0;374}375}376ar[r].isDirty = false;377ar[r].mipsReg = MIPS_REG_INVALID;378}379380void ArmRegCache::DiscardR(MIPSGPReg mipsReg) {381const RegMIPSLoc prevLoc = mr[mipsReg].loc;382if (prevLoc == ML_ARMREG || prevLoc == ML_ARMREG_AS_PTR || prevLoc == ML_ARMREG_IMM) {383ARMReg armReg = mr[mipsReg].reg;384ar[armReg].isDirty = false;385ar[armReg].mipsReg = MIPS_REG_INVALID;386mr[mipsReg].reg = INVALID_REG;387if (mipsReg == MIPS_REG_ZERO) {388mr[mipsReg].loc = ML_IMM;389} else {390mr[mipsReg].loc = ML_MEM;391}392mr[mipsReg].imm = 0;393}394if (prevLoc == ML_IMM && mipsReg != MIPS_REG_ZERO) {395mr[mipsReg].loc = ML_MEM;396mr[mipsReg].imm = 0;397}398}399400void ArmRegCache::FlushR(MIPSGPReg r) {401switch (mr[r].loc) {402case ML_IMM:403// IMM is always "dirty".404if (r != MIPS_REG_ZERO) {405SetRegImm(SCRATCHREG1, mr[r].imm);406emit_->STR(SCRATCHREG1, CTXREG, GetMipsRegOffset(r));407}408break;409410case ML_ARMREG:411case ML_ARMREG_IMM:412if (mr[r].reg == INVALID_REG) {413ERROR_LOG_REPORT(Log::JIT, "FlushR: MipsReg %d had bad ArmReg", r);414}415if (ar[mr[r].reg].isDirty) {416if (r != MIPS_REG_ZERO) {417emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));418}419ar[mr[r].reg].isDirty = false;420}421ar[mr[r].reg].mipsReg = MIPS_REG_INVALID;422break;423424case ML_ARMREG_AS_PTR:425// Never dirty.426if (ar[mr[r].reg].isDirty) {427ERROR_LOG_REPORT(Log::JIT, "ARMREG_AS_PTR cannot be dirty (yet)");428}429ar[mr[r].reg].mipsReg = MIPS_REG_INVALID;430break;431432case ML_MEM:433// Already there, nothing to do.434break;435436default:437ERROR_LOG_REPORT(Log::JIT, "FlushR: MipsReg %d with invalid location %d", r, mr[r].loc);438break;439}440if (r == MIPS_REG_ZERO) {441mr[r].loc = ML_IMM;442} else {443mr[r].loc = ML_MEM;444}445mr[r].reg = INVALID_REG;446mr[r].imm = 0;447}448449// Note: if allowFlushImm is set, this also flushes imms while checking the sequence.450int ArmRegCache::FlushGetSequential(MIPSGPReg startMipsReg, bool allowFlushImm) {451// Only start a sequence on a dirty armreg.452// TODO: Could also start with an imm?453const auto &startMipsInfo = mr[startMipsReg];454if ((startMipsInfo.loc != ML_ARMREG && startMipsInfo.loc != ML_ARMREG_IMM) || startMipsInfo.reg == INVALID_REG || !ar[startMipsInfo.reg].isDirty) {455return 0;456}457458int allocCount;459const ARMReg *allocOrder = GetMIPSAllocationOrder(allocCount);460461int c = 1;462// The sequence needs to have ascending arm regs for STMIA.463int lastArmReg = startMipsInfo.reg;464// Can't use HI/LO, only regs in the main r[] array.465for (int r = (int)startMipsReg + 1; r < 32; ++r) {466if ((mr[r].loc == ML_ARMREG || mr[r].loc == ML_ARMREG_IMM) && mr[r].reg != INVALID_REG) {467if ((int)mr[r].reg > lastArmReg && ar[mr[r].reg].isDirty) {468++c;469lastArmReg = mr[r].reg;470continue;471}472// If we're not allowed to flush imms, don't even consider them.473} else if (allowFlushImm && mr[r].loc == ML_IMM && MIPSGPReg(r) != MIPS_REG_ZERO) {474// Okay, let's search for a free (and later) reg to put this imm into.475bool found = false;476for (int j = 0; j < allocCount; ++j) {477ARMReg immReg = allocOrder[j];478if ((int)immReg > lastArmReg && ar[immReg].mipsReg == MIPS_REG_INVALID) {479++c;480lastArmReg = immReg;481482// Even if the sequence fails, we'll need it in a reg anyway, might as well be this one.483MapRegTo(immReg, MIPSGPReg(r), 0);484found = true;485break;486}487}488if (found) {489continue;490}491}492493// If it didn't hit a continue above, the chain is over.494// There's no way to skip a slot with STMIA.495break;496}497498return c;499}500501void ArmRegCache::FlushAll() {502// ADD + STMIA is probably better than STR + STR, so let's merge 2 into a STMIA.503const int minSequential = 2;504505// Let's try to put things in order and use STMIA.506// First we have to save imms. We have to use a separate loop because otherwise507// we would overwrite existing regs, and other code assumes FlushAll() won't do that.508for (int i = 0; i < NUM_MIPSREG; i++) {509MIPSGPReg mipsReg = MIPSGPReg(i);510511// This happens to also flush imms to regs as much as possible.512int c = FlushGetSequential(mipsReg, true);513if (c >= minSequential) {514// Skip the next c (adjust down 1 because the loop increments.)515i += c - 1;516}517}518519// Okay, now the real deal: this time NOT flushing imms.520for (int i = 0; i < NUM_MIPSREG; i++) {521MIPSGPReg mipsReg = MIPSGPReg(i);522523int c = FlushGetSequential(mipsReg, false);524if (c >= minSequential) {525u16 regs = 0;526for (int j = 0; j < c; ++j) {527regs |= 1 << mr[i + j].reg;528}529530emit_->ADD(SCRATCHREG1, CTXREG, GetMipsRegOffset(mipsReg));531emit_->STMBitmask(SCRATCHREG1, true, false, false, regs);532533// Okay, those are all done now, discard them.534for (int j = 0; j < c; ++j) {535DiscardR(MIPSGPReg(i + j));536}537// Skip the next c (adjust down 1 because the loop increments.)538i += c - 1;539} else {540FlushR(mipsReg);541}542}543// Sanity check544for (int i = 0; i < NUM_ARMREG; i++) {545if (ar[i].mipsReg != MIPS_REG_INVALID) {546ERROR_LOG_REPORT(Log::JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);547}548}549}550551void ArmRegCache::SetImm(MIPSGPReg r, u32 immVal) {552if (r == MIPS_REG_ZERO && immVal != 0) {553ERROR_LOG_REPORT(Log::JIT, "Trying to set immediate %08x to r0 at %08x", immVal, compilerPC_);554return;555}556557if (mr[r].loc == ML_ARMREG_IMM && mr[r].imm == immVal) {558// Already have that value, let's keep it in the reg.559return;560}561// Zap existing value if cached in a reg562if (mr[r].reg != INVALID_REG) {563ar[mr[r].reg].mipsReg = MIPS_REG_INVALID;564ar[mr[r].reg].isDirty = false;565}566mr[r].loc = ML_IMM;567mr[r].imm = immVal;568mr[r].reg = INVALID_REG;569}570571bool ArmRegCache::IsImm(MIPSGPReg r) const {572if (r == MIPS_REG_ZERO) return true;573return mr[r].loc == ML_IMM || mr[r].loc == ML_ARMREG_IMM;574}575576u32 ArmRegCache::GetImm(MIPSGPReg r) const {577if (r == MIPS_REG_ZERO) return 0;578if (mr[r].loc != ML_IMM && mr[r].loc != ML_ARMREG_IMM) {579ERROR_LOG_REPORT(Log::JIT, "Trying to get imm from non-imm register %i", r);580}581return mr[r].imm;582}583584int ArmRegCache::GetMipsRegOffset(MIPSGPReg r) {585if (r < 32)586return r * 4;587switch (r) {588case MIPS_REG_HI:589return offsetof(MIPSState, hi);590case MIPS_REG_LO:591return offsetof(MIPSState, lo);592case MIPS_REG_FPCOND:593return offsetof(MIPSState, fpcond);594case MIPS_REG_VFPUCC:595return offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_CC]);596default:597ERROR_LOG_REPORT(Log::JIT, "bad mips register %i", r);598return 0; // or what?599}600}601602void ArmRegCache::SpillLock(MIPSGPReg r1, MIPSGPReg r2, MIPSGPReg r3, MIPSGPReg r4) {603mr[r1].spillLock = true;604if (r2 != MIPS_REG_INVALID) mr[r2].spillLock = true;605if (r3 != MIPS_REG_INVALID) mr[r3].spillLock = true;606if (r4 != MIPS_REG_INVALID) mr[r4].spillLock = true;607}608609void ArmRegCache::ReleaseSpillLocks() {610for (int i = 0; i < NUM_MIPSREG; i++) {611mr[i].spillLock = false;612}613}614615void ArmRegCache::ReleaseSpillLock(MIPSGPReg reg) {616mr[reg].spillLock = false;617}618619ARMReg ArmRegCache::R(MIPSGPReg mipsReg) {620if (mr[mipsReg].loc == ML_ARMREG || mr[mipsReg].loc == ML_ARMREG_IMM) {621return (ARMReg)mr[mipsReg].reg;622} else {623ERROR_LOG_REPORT(Log::JIT, "Reg %i not in arm reg. compilerPC = %08x", mipsReg, compilerPC_);624return INVALID_REG; // BAAAD625}626}627628ARMReg ArmRegCache::RPtr(MIPSGPReg mipsReg) {629if (mr[mipsReg].loc == ML_ARMREG_AS_PTR) {630return (ARMReg)mr[mipsReg].reg;631} else {632ERROR_LOG_REPORT(Log::JIT, "Reg %i not in arm reg as pointer. compilerPC = %08x", mipsReg, compilerPC_);633return INVALID_REG; // BAAAD634}635}636637#endif // PPSSPP_ARCH(ARM)638639640