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Path: blob/master/Core/MIPS/ARM64/Arm64IRCompSystem.cpp
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "ppsspp_config.h"18// In other words, PPSSPP_ARCH(ARM64) || DISASM_ALL.19#if PPSSPP_ARCH(ARM64) || (PPSSPP_PLATFORM(WINDOWS) && !defined(__LIBRETRO__))2021#include "Common/Profiler/Profiler.h"22#include "Core/Core.h"23#include "Core/Debugger/Breakpoints.h"24#include "Core/HLE/HLE.h"25#include "Core/HLE/ReplaceTables.h"26#include "Core/MemMap.h"27#include "Core/MIPS/MIPSAnalyst.h"28#include "Core/MIPS/IR/IRInterpreter.h"29#include "Core/MIPS/ARM64/Arm64IRJit.h"30#include "Core/MIPS/ARM64/Arm64IRRegCache.h"3132// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc.33//34// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.35// Currently known non working ones should have DISABLE. No flags because that's in IR already.3637// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }38#define CONDITIONAL_DISABLE {}39#define DISABLE { CompIR_Generic(inst); return; }40#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }4142namespace MIPSComp {4344using namespace Arm64Gen;45using namespace Arm64IRJitConstants;4647void Arm64JitBackend::CompIR_Basic(IRInst inst) {48CONDITIONAL_DISABLE;4950switch (inst.op) {51case IROp::Downcount:52SUBI2R(DOWNCOUNTREG, DOWNCOUNTREG, (s64)(s32)inst.constant, SCRATCH1);53break;5455case IROp::SetConst:56regs_.SetGPRImm(inst.dest, inst.constant);57break;5859case IROp::SetConstF:60{61regs_.Map(inst);62float f;63memcpy(&f, &inst.constant, sizeof(f));64fp_.MOVI2F(regs_.F(inst.dest), f, SCRATCH1);65break;66}6768case IROp::SetPC:69regs_.Map(inst);70MovToPC(regs_.R(inst.src1));71break;7273case IROp::SetPCConst:74lastConstPC_ = inst.constant;75MOVI2R(SCRATCH1, inst.constant);76MovToPC(SCRATCH1);77break;7879default:80INVALIDOP;81break;82}83}8485void Arm64JitBackend::CompIR_Breakpoint(IRInst inst) {86CONDITIONAL_DISABLE;8788switch (inst.op) {89case IROp::Breakpoint:90{91FlushAll();92// Note: the constant could be a delay slot.93MOVI2R(W0, inst.constant);94QuickCallFunction(SCRATCH2_64, &IRRunBreakpoint);9596ptrdiff_t distance = dispatcherCheckCoreState_ - GetCodePointer();97if (distance >= -0x100000 && distance < 0x100000) {98CBNZ(W0, dispatcherCheckCoreState_);99} else {100FixupBranch keepOnKeepingOn = CBZ(W0);101B(dispatcherCheckCoreState_);102SetJumpTarget(keepOnKeepingOn);103}104break;105}106107case IROp::MemoryCheck:108if (regs_.IsGPRImm(inst.src1)) {109uint32_t iaddr = regs_.GetGPRImm(inst.src1) + inst.constant;110uint32_t checkedPC = lastConstPC_ + inst.dest;111int size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);112if (size == 0) {113checkedPC += 4;114size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);115}116bool isWrite = MIPSAnalyst::IsOpMemoryWrite(checkedPC);117118MemCheck check;119if (CBreakPoints::GetMemCheckInRange(iaddr, size, &check)) {120if (!(check.cond & MEMCHECK_READ) && !isWrite)121break;122if (!(check.cond & (MEMCHECK_WRITE | MEMCHECK_WRITE_ONCHANGE)) && isWrite)123break;124125// We need to flush, or conditions and log expressions will see old register values.126FlushAll();127128MOVI2R(W0, checkedPC);129MOVI2R(W1, iaddr);130QuickCallFunction(SCRATCH2_64, &IRRunMemCheck);131132ptrdiff_t distance = dispatcherCheckCoreState_ - GetCodePointer();133if (distance >= -0x100000 && distance < 0x100000) {134CBNZ(W0, dispatcherCheckCoreState_);135} else {136FixupBranch keepOnKeepingOn = CBZ(W0);137B(dispatcherCheckCoreState_);138SetJumpTarget(keepOnKeepingOn);139}140}141} else {142uint32_t checkedPC = lastConstPC_ + inst.dest;143int size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);144if (size == 0) {145checkedPC += 4;146size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);147}148bool isWrite = MIPSAnalyst::IsOpMemoryWrite(checkedPC);149150const auto memchecks = CBreakPoints::GetMemCheckRanges(isWrite);151// We can trivially skip if there are no checks for this type (i.e. read vs write.)152if (memchecks.empty())153break;154155ARM64Reg addrBase = regs_.MapGPR(inst.src1);156ADDI2R(SCRATCH1, addrBase, inst.constant, SCRATCH2);157158// We need to flush, or conditions and log expressions will see old register values.159FlushAll();160161std::vector<FixupBranch> hitChecks;162for (auto it : memchecks) {163if (it.end != 0) {164CMPI2R(SCRATCH1, it.start - size, SCRATCH2);165MOVI2R(SCRATCH2, it.end);166CCMP(SCRATCH1, SCRATCH2, 0xF, CC_HI);167hitChecks.push_back(B(CC_LO));168} else {169CMPI2R(SCRATCH1, it.start, SCRATCH2);170hitChecks.push_back(B(CC_EQ));171}172}173174FixupBranch noHits = B();175176// Okay, now land any hit here.177for (auto &fixup : hitChecks)178SetJumpTarget(fixup);179hitChecks.clear();180181MOVI2R(W0, checkedPC);182MOV(W1, SCRATCH1);183QuickCallFunction(SCRATCH2_64, &IRRunMemCheck);184185ptrdiff_t distance = dispatcherCheckCoreState_ - GetCodePointer();186if (distance >= -0x100000 && distance < 0x100000) {187CBNZ(W0, dispatcherCheckCoreState_);188} else {189FixupBranch keepOnKeepingOn = CBZ(W0);190B(dispatcherCheckCoreState_);191SetJumpTarget(keepOnKeepingOn);192}193194SetJumpTarget(noHits);195}196break;197198default:199INVALIDOP;200break;201}202}203204void Arm64JitBackend::CompIR_System(IRInst inst) {205CONDITIONAL_DISABLE;206207switch (inst.op) {208case IROp::Syscall:209FlushAll();210SaveStaticRegisters();211212WriteDebugProfilerStatus(IRProfilerStatus::SYSCALL);213#ifdef USE_PROFILER214// When profiling, we can't skip CallSyscall, since it times syscalls.215MOVI2R(W0, inst.constant);216QuickCallFunction(SCRATCH2_64, &CallSyscall);217#else218// Skip the CallSyscall where possible.219{220MIPSOpcode op(inst.constant);221void *quickFunc = GetQuickSyscallFunc(op);222if (quickFunc) {223MOVP2R(X0, GetSyscallFuncPointer(op));224QuickCallFunction(SCRATCH2_64, (const u8 *)quickFunc);225} else {226MOVI2R(W0, inst.constant);227QuickCallFunction(SCRATCH2_64, &CallSyscall);228}229}230#endif231232WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);233LoadStaticRegisters();234// This is always followed by an ExitToPC, where we check coreState.235break;236237case IROp::CallReplacement:238FlushAll();239SaveStaticRegisters();240WriteDebugProfilerStatus(IRProfilerStatus::REPLACEMENT);241QuickCallFunction(SCRATCH2_64, GetReplacementFunc(inst.constant)->replaceFunc);242WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);243LoadStaticRegisters();244245// Absolute value the result and subtract.246CMP(W0, 0);247CSNEG(SCRATCH1, W0, W0, CC_PL);248SUB(DOWNCOUNTREG, DOWNCOUNTREG, SCRATCH1);249250// W0 might be the mapped reg, but there's only one.251// Set dest reg to the sign of the result.252regs_.Map(inst);253ASR(regs_.R(inst.dest), W0, 31);254break;255256case IROp::Break:257FlushAll();258// This doesn't naturally have restore/apply around it.259RestoreRoundingMode(true);260SaveStaticRegisters();261MovFromPC(W0);262QuickCallFunction(SCRATCH2_64, &Core_Break);263LoadStaticRegisters();264ApplyRoundingMode(true);265MovFromPC(SCRATCH1);266ADDI2R(SCRATCH1, SCRATCH1, 4, SCRATCH2);267B(dispatcherPCInSCRATCH1_);268break;269270default:271INVALIDOP;272break;273}274}275276void Arm64JitBackend::CompIR_Transfer(IRInst inst) {277CONDITIONAL_DISABLE;278279switch (inst.op) {280case IROp::SetCtrlVFPU:281regs_.SetGPRImm(IRREG_VFPU_CTRL_BASE + inst.dest, inst.constant);282break;283284case IROp::SetCtrlVFPUReg:285regs_.Map(inst);286MOV(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.R(inst.src1));287break;288289case IROp::SetCtrlVFPUFReg:290regs_.Map(inst);291fp_.FMOV(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.F(inst.src1));292break;293294case IROp::FpCondFromReg:295regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });296MOV(regs_.R(IRREG_FPCOND), regs_.R(inst.src1));297break;298299case IROp::FpCondToReg:300regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });301MOV(regs_.R(inst.dest), regs_.R(IRREG_FPCOND));302break;303304case IROp::FpCtrlFromReg:305regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });306ANDI2R(SCRATCH1, regs_.R(inst.src1), 0x0181FFFF, SCRATCH2);307// Extract the new fpcond value.308UBFX(regs_.R(IRREG_FPCOND), SCRATCH1, 23, 1);309STR(INDEX_UNSIGNED, SCRATCH1, CTXREG, IRREG_FCR31 * 4);310break;311312case IROp::FpCtrlToReg:313regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });314// Load fcr31 and clear the fpcond bit.315LDR(INDEX_UNSIGNED, regs_.R(inst.dest), CTXREG, IRREG_FCR31 * 4);316BFI(regs_.R(inst.dest), regs_.R(IRREG_FPCOND), 23, 1);317// Also update mips->fcr31 while we're here.318STR(INDEX_UNSIGNED, regs_.R(inst.dest), CTXREG, IRREG_FCR31 * 4);319break;320321case IROp::VfpuCtrlToReg:322regs_.Map(inst);323MOV(regs_.R(inst.dest), regs_.R(IRREG_VFPU_CTRL_BASE + inst.src1));324break;325326case IROp::FMovFromGPR:327if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) {328regs_.MapFPR(inst.dest, MIPSMap::NOINIT);329fp_.MOVI2F(regs_.F(inst.dest), 0.0f, SCRATCH1);330} else {331regs_.Map(inst);332fp_.FMOV(regs_.F(inst.dest), regs_.R(inst.src1));333}334break;335336case IROp::FMovToGPR:337regs_.Map(inst);338fp_.FMOV(regs_.R(inst.dest), regs_.F(inst.src1));339break;340341default:342INVALIDOP;343break;344}345}346347void Arm64JitBackend::CompIR_ValidateAddress(IRInst inst) {348CONDITIONAL_DISABLE;349350bool isWrite = inst.src2 & 1;351int alignment = 0;352switch (inst.op) {353case IROp::ValidateAddress8:354alignment = 1;355break;356357case IROp::ValidateAddress16:358alignment = 2;359break;360361case IROp::ValidateAddress32:362alignment = 4;363break;364365case IROp::ValidateAddress128:366alignment = 16;367break;368369default:370INVALIDOP;371break;372}373374if (regs_.IsGPRMappedAsPointer(inst.src1)) {375if (!jo.enablePointerify) {376SUB(SCRATCH1_64, regs_.RPtr(inst.src1), MEMBASEREG);377ADDI2R(SCRATCH1, SCRATCH1, inst.constant, SCRATCH2);378} else {379ADDI2R(SCRATCH1, regs_.R(inst.src1), inst.constant, SCRATCH2);380}381} else {382regs_.Map(inst);383ADDI2R(SCRATCH1, regs_.R(inst.src1), inst.constant, SCRATCH2);384}385ANDI2R(SCRATCH1, SCRATCH1, 0x3FFFFFFF, SCRATCH2);386387std::vector<FixupBranch> validJumps;388389FixupBranch unaligned;390if (alignment == 2) {391unaligned = TBNZ(SCRATCH1, 0);392} else if (alignment != 1) {393TSTI2R(SCRATCH1, alignment - 1, SCRATCH2);394unaligned = B(CC_NEQ);395}396397CMPI2R(SCRATCH1, PSP_GetUserMemoryEnd() - alignment, SCRATCH2);398FixupBranch tooHighRAM = B(CC_HI);399CMPI2R(SCRATCH1, PSP_GetKernelMemoryBase(), SCRATCH2);400validJumps.push_back(B(CC_HS));401402CMPI2R(SCRATCH1, PSP_GetVidMemEnd() - alignment, SCRATCH2);403FixupBranch tooHighVid = B(CC_HI);404CMPI2R(SCRATCH1, PSP_GetVidMemBase(), SCRATCH2);405validJumps.push_back(B(CC_HS));406407CMPI2R(SCRATCH1, PSP_GetScratchpadMemoryEnd() - alignment, SCRATCH2);408FixupBranch tooHighScratch = B(CC_HI);409CMPI2R(SCRATCH1, PSP_GetScratchpadMemoryBase(), SCRATCH2);410validJumps.push_back(B(CC_HS));411412if (alignment != 1)413SetJumpTarget(unaligned);414SetJumpTarget(tooHighRAM);415SetJumpTarget(tooHighVid);416SetJumpTarget(tooHighScratch);417418// If we got here, something unusual and bad happened, so we'll always go back to the dispatcher.419// Because of that, we can avoid flushing outside this case.420auto regsCopy = regs_;421regsCopy.FlushAll();422423// Ignores the return value, always returns to the dispatcher.424// Otherwise would need a thunk to restore regs.425MOV(W0, SCRATCH1);426MOVI2R(W1, alignment);427MOVI2R(W2, isWrite ? 1 : 0);428QuickCallFunction(SCRATCH2, &ReportBadAddress);429B(dispatcherCheckCoreState_);430431for (FixupBranch &b : validJumps)432SetJumpTarget(b);433}434435} // namespace MIPSComp436437#endif438439440