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Path: blob/master/Core/MIPS/IR/IRCompBranch.cpp
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// Copyright (c) 2012- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "Common/Data/Convert/SmallDataConvert.h"18#include "Common/Profiler/Profiler.h"1920#include "Core/Reporting.h"21#include "Core/Config.h"22#include "Core/MemMap.h"23#include "Core/HLE/HLE.h"24#include "Core/HLE/HLETables.h"2526#include "Core/MIPS/MIPS.h"27#include "Core/MIPS/MIPSCodeUtils.h"28#include "Core/MIPS/MIPSAnalyst.h"29#include "Core/MIPS/MIPSTables.h"3031#include "Core/MIPS/IR/IRFrontend.h"32#include "Core/MIPS/JitCommon/JitBlockCache.h"3334#define _RS MIPS_GET_RS(op)35#define _RT MIPS_GET_RT(op)36#define _RD MIPS_GET_RD(op)37#define _FS MIPS_GET_FS(op)38#define _FT MIPS_GET_FT(op)39#define _FD MIPS_GET_FD(op)40#define _SA MIPS_GET_SA(op)41#define _POS ((op>> 6) & 0x1F)42#define _SIZE ((op>>11) & 0x1F)43#define _IMM26 (op & 0x03FFFFFF)44#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))45#define TARGET26 (_IMM26 << 2)4647#define LOOPOPTIMIZATION 04849#define MIPS_IS_BREAK(op) (((op) & 0xFC00003F) == 13)5051using namespace MIPSAnalyst;5253namespace MIPSComp54{5556void IRFrontend::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely) {57if (js.inDelaySlot) {58ERROR_LOG_REPORT(Log::JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);59return;60}61int offset = TARGET16;62MIPSGPReg rt = _RT;63MIPSGPReg rs = _RS;64u32 targetAddr = GetCompilerPC() + offset + 4;6566BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), false, likely);67branchInfo.delaySlotIsNice = IsDelaySlotNiceReg(op, branchInfo.delaySlotOp, rt, rs);6869js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);7071// Often, div/divu are followed by a likely "break" if the divisor was zero.72// Stalling is not really useful for us, so we optimize this out.73if (likely && offset == 4 && MIPS_IS_BREAK(branchInfo.delaySlotOp)) {74// Okay, let's not actually branch at all. We're done here.75EatInstruction(branchInfo.delaySlotOp);76// Let's not double-count the downcount, though.77js.downcountAmount--;78return;79}8081MIPSGPReg lhs = rs;82MIPSGPReg rhs = rt;83if (!branchInfo.delaySlotIsNice && !likely) { // if likely, we don't need this84if (rs != 0) {85ir.Write(IROp::Mov, IRTEMP_LHS, rs);86lhs = (MIPSGPReg)IRTEMP_LHS;87}88if (rt != 0) {89ir.Write(IROp::Mov, IRTEMP_RHS, rt);90rhs = (MIPSGPReg)IRTEMP_RHS;91}92}9394if (!likely && !branchInfo.delaySlotIsBranch)95CompileDelaySlot();9697int dcAmount = js.downcountAmount;98ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));99js.downcountAmount = 0;100101FlushAll();102ir.Write(ComparisonToExit(cc), ir.AddConstant(ResolveNotTakenTarget(branchInfo)), lhs, rhs);103// This makes the block "impure" :(104if (likely && !branchInfo.delaySlotIsBranch)105CompileDelaySlot();106if (branchInfo.delaySlotIsBranch) {107// We still link when the branch is taken (targetAddr case.)108// Remember, it's from the perspective of the delay slot, so +12.109if ((branchInfo.delaySlotInfo & OUT_RA) != 0)110ir.WriteSetConstant(MIPS_REG_RA, GetCompilerPC() + 12);111if ((branchInfo.delaySlotInfo & OUT_RD) != 0)112ir.WriteSetConstant(MIPS_GET_RD(branchInfo.delaySlotOp), GetCompilerPC() + 12);113}114115FlushAll();116ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));117118// Account for the delay slot.119js.compilerPC += 4;120js.compiling = false;121}122123void IRFrontend::BranchRSZeroComp(MIPSOpcode op, IRComparison cc, bool andLink, bool likely) {124if (js.inDelaySlot) {125ERROR_LOG_REPORT(Log::JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);126return;127}128int offset = TARGET16;129MIPSGPReg rs = _RS;130u32 targetAddr = GetCompilerPC() + offset + 4;131132BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), andLink, likely);133branchInfo.delaySlotIsNice = IsDelaySlotNiceReg(op, branchInfo.delaySlotOp, rs);134135js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);136137MIPSGPReg lhs = rs;138if (!branchInfo.delaySlotIsNice) { // if likely, we don't need this139ir.Write(IROp::Mov, IRTEMP_LHS, rs);140lhs = (MIPSGPReg)IRTEMP_LHS;141}142if (andLink)143ir.WriteSetConstant(MIPS_REG_RA, GetCompilerPC() + 8);144145if (!likely && !branchInfo.delaySlotIsBranch)146CompileDelaySlot();147148int dcAmount = js.downcountAmount;149ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));150js.downcountAmount = 0;151152FlushAll();153ir.Write(ComparisonToExit(cc), ir.AddConstant(ResolveNotTakenTarget(branchInfo)), lhs);154if (likely && !branchInfo.delaySlotIsBranch)155CompileDelaySlot();156if (branchInfo.delaySlotIsBranch) {157// We still link when the branch is taken (targetAddr case.)158// Remember, it's from the perspective of the delay slot, so +12.159if ((branchInfo.delaySlotInfo & OUT_RA) != 0)160ir.WriteSetConstant(MIPS_REG_RA, GetCompilerPC() + 12);161if ((branchInfo.delaySlotInfo & OUT_RD) != 0)162ir.WriteSetConstant(MIPS_GET_RD(branchInfo.delaySlotOp), GetCompilerPC() + 12);163}164165// Taken166FlushAll();167ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));168169// Account for the delay slot.170js.compilerPC += 4;171js.compiling = false;172}173174void IRFrontend::Comp_RelBranch(MIPSOpcode op) {175// The CC flags here should be opposite of the actual branch because they skip the branching action.176switch (op >> 26) {177case 4: BranchRSRTComp(op, IRComparison::NotEqual, false); break;//beq178case 5: BranchRSRTComp(op, IRComparison::Equal, false); break;//bne179180case 6: BranchRSZeroComp(op, IRComparison::Greater, false, false); break;//blez181case 7: BranchRSZeroComp(op, IRComparison::LessEqual, false, false); break;//bgtz182183case 20: BranchRSRTComp(op, IRComparison::NotEqual, true); break;//beql184case 21: BranchRSRTComp(op, IRComparison::Equal, true); break;//bnel185186case 22: BranchRSZeroComp(op, IRComparison::Greater, false, true); break;//blezl187case 23: BranchRSZeroComp(op, IRComparison::LessEqual, false, true); break;//bgtzl188189default:190_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");191break;192}193}194195void IRFrontend::Comp_RelBranchRI(MIPSOpcode op) {196switch ((op >> 16) & 0x1F) {197case 0: BranchRSZeroComp(op, IRComparison::GreaterEqual, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz198case 1: BranchRSZeroComp(op, IRComparison::Less, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez199case 2: BranchRSZeroComp(op, IRComparison::GreaterEqual, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl200case 3: BranchRSZeroComp(op, IRComparison::Less, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl201case 16: BranchRSZeroComp(op, IRComparison::GreaterEqual, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal202case 17: BranchRSZeroComp(op, IRComparison::Less, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal203case 18: BranchRSZeroComp(op, IRComparison::GreaterEqual, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall204case 19: BranchRSZeroComp(op, IRComparison::Less, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall205default:206_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");207break;208}209}210211// If likely is set, discard the branch slot if NOT taken.212void IRFrontend::BranchFPFlag(MIPSOpcode op, IRComparison cc, bool likely) {213if (js.inDelaySlot) {214ERROR_LOG_REPORT(Log::JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);215return;216}217int offset = TARGET16;218u32 targetAddr = GetCompilerPC() + offset + 4;219220BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), false, likely);221222ir.Write(IROp::FpCondToReg, IRTEMP_LHS);223if (!likely && !branchInfo.delaySlotIsBranch)224CompileDelaySlot();225226int dcAmount = js.downcountAmount;227ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));228js.downcountAmount = 0;229230FlushAll();231// Not taken232ir.Write(ComparisonToExit(cc), ir.AddConstant(ResolveNotTakenTarget(branchInfo)), IRTEMP_LHS, 0);233// Taken234if (likely && !branchInfo.delaySlotIsBranch)235CompileDelaySlot();236if (branchInfo.delaySlotIsBranch) {237// We still link when the branch is taken (targetAddr case.)238// Remember, it's from the perspective of the delay slot, so +12.239if ((branchInfo.delaySlotInfo & OUT_RA) != 0)240ir.WriteSetConstant(MIPS_REG_RA, GetCompilerPC() + 12);241if ((branchInfo.delaySlotInfo & OUT_RD) != 0)242ir.WriteSetConstant(MIPS_GET_RD(branchInfo.delaySlotOp), GetCompilerPC() + 12);243}244245FlushAll();246ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));247248// Account for the delay slot.249js.compilerPC += 4;250js.compiling = false;251}252253void IRFrontend::Comp_FPUBranch(MIPSOpcode op) {254switch((op >> 16) & 0x1f) {255case 0: BranchFPFlag(op, IRComparison::NotEqual, false); break; // bc1f256case 1: BranchFPFlag(op, IRComparison::Equal, false); break; // bc1t257case 2: BranchFPFlag(op, IRComparison::NotEqual, true); break; // bc1fl258case 3: BranchFPFlag(op, IRComparison::Equal, true); break; // bc1tl259default:260_dbg_assert_msg_( 0, "Trying to interpret instruction that can't be interpreted");261break;262}263}264265// If likely is set, discard the branch slot if NOT taken.266void IRFrontend::BranchVFPUFlag(MIPSOpcode op, IRComparison cc, bool likely) {267if (js.inDelaySlot) {268ERROR_LOG_REPORT(Log::JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);269return;270}271int offset = TARGET16;272u32 targetAddr = GetCompilerPC() + offset + 4;273274BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), false, likely);275276js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);277ir.Write(IROp::VfpuCtrlToReg, IRTEMP_LHS, VFPU_CTRL_CC);278279// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)280// The behavior is undefined - the CPU may take the second branch even if the first one passes.281// However, it does consistently try each branch, which these games seem to expect.282if (!likely && !branchInfo.delaySlotIsBranch)283CompileDelaySlot();284285int dcAmount = js.downcountAmount;286ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));287js.downcountAmount = 0;288289int imm3 = (op >> 18) & 7;290291ir.Write(IROp::AndConst, IRTEMP_LHS, IRTEMP_LHS, ir.AddConstant(1 << imm3));292FlushAll();293ir.Write(ComparisonToExit(cc), ir.AddConstant(ResolveNotTakenTarget(branchInfo)), IRTEMP_LHS, 0);294295if (likely && !branchInfo.delaySlotIsBranch)296CompileDelaySlot();297if (branchInfo.delaySlotIsBranch) {298// We still link when the branch is taken (targetAddr case.)299// Remember, it's from the perspective of the delay slot, so +12.300if ((branchInfo.delaySlotInfo & OUT_RA) != 0)301ir.WriteSetConstant(MIPS_REG_RA, GetCompilerPC() + 12);302if ((branchInfo.delaySlotInfo & OUT_RD) != 0)303ir.WriteSetConstant(MIPS_GET_RD(branchInfo.delaySlotOp), GetCompilerPC() + 12);304}305306// Taken307FlushAll();308ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));309310// Account for the delay slot.311js.compilerPC += 4;312js.compiling = false;313}314315void IRFrontend::Comp_VBranch(MIPSOpcode op) {316switch ((op >> 16) & 3) {317case 0: BranchVFPUFlag(op, IRComparison::NotEqual, false); break; // bvf318case 1: BranchVFPUFlag(op, IRComparison::Equal, false); break; // bvt319case 2: BranchVFPUFlag(op, IRComparison::NotEqual, true); break; // bvfl320case 3: BranchVFPUFlag(op, IRComparison::Equal, true); break; // bvtl321}322}323324void IRFrontend::Comp_Jump(MIPSOpcode op) {325if (js.inDelaySlot) {326ERROR_LOG_REPORT(Log::JIT, "Branch in Jump delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);327return;328}329330u32 off = TARGET26;331u32 targetAddr = (GetCompilerPC() & 0xF0000000) | off;332333// Might be a stubbed address or something?334if (!Memory::IsValidAddress(targetAddr)) {335// If preloading, flush - this block will likely be fixed later.336if (js.preloading)337js.cancel = true;338else339ERROR_LOG_REPORT(Log::JIT, "Jump to invalid address: %08x", targetAddr);340// TODO: Mark this block dirty or something? May be indication it will be changed by imports.341// Continue so the block gets completed and crashes properly.342}343344switch (op >> 26) {345case 2: //j346CompileDelaySlot();347break;348349case 3: //jal350ir.WriteSetConstant(MIPS_REG_RA, GetCompilerPC() + 8);351CompileDelaySlot();352break;353354default:355_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");356break;357}358359int dcAmount = js.downcountAmount;360ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));361js.downcountAmount = 0;362363FlushAll();364ir.Write(IROp::ExitToConst, ir.AddConstant(targetAddr));365366// Account for the delay slot.367js.compilerPC += 4;368js.compiling = false;369}370371void IRFrontend::Comp_JumpReg(MIPSOpcode op) {372if (js.inDelaySlot) {373ERROR_LOG_REPORT(Log::JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);374return;375}376MIPSGPReg rs = _RS;377MIPSGPReg rd = _RD;378bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;379380MIPSOpcode delaySlotOp = GetOffsetInstruction(1);381js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);382bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);383if (andLink && rs == rd)384delaySlotIsNice = false;385386int destReg;387if (IsSyscall(delaySlotOp)) {388ir.Write(IROp::SetPC, 0, rs);389if (andLink)390ir.WriteSetConstant(rd, GetCompilerPC() + 8);391CompileDelaySlot();392// Syscall (the delay slot) does FlushAll.393394// Account for the delay slot itself in total bytes.395js.compilerPC += 4;396return; // Syscall (delay slot) wrote exit code.397} else if (delaySlotIsNice) {398if (andLink)399ir.WriteSetConstant(rd, GetCompilerPC() + 8);400CompileDelaySlot();401destReg = rs; // Safe because FlushAll doesn't change any regs402FlushAll();403} else {404// Bad delay slot.405ir.Write(IROp::Mov, IRTEMP_LHS, rs);406destReg = IRTEMP_LHS;407if (andLink)408ir.WriteSetConstant(rd, GetCompilerPC() + 8);409CompileDelaySlot();410FlushAll();411}412413switch (op & 0x3f)414{415case 8: //jr416break;417case 9: //jalr418break;419default:420_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");421break;422}423424int dcAmount = js.downcountAmount;425ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));426js.downcountAmount = 0;427428ir.Write(IROp::ExitToReg, 0, destReg, 0);429430// Account for the delay slot.431js.compilerPC += 4;432js.compiling = false;433}434435void IRFrontend::Comp_Syscall(MIPSOpcode op) {436// Note: If we're in a delay slot, this is off by one compared to the interpreter.437int dcAmount = js.downcountAmount + (js.inDelaySlot ? -1 : 0);438ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount));439js.downcountAmount = 0;440441// If not in a delay slot, we need to update PC.442if (!js.inDelaySlot) {443ir.Write(IROp::SetPCConst, 0, ir.AddConstant(GetCompilerPC() + 4));444}445446FlushAll();447448RestoreRoundingMode();449ir.Write(IROp::Syscall, 0, ir.AddConstant(op.encoding));450ApplyRoundingMode();451ir.Write(IROp::ExitToPC);452453js.compiling = false;454}455456void IRFrontend::Comp_Break(MIPSOpcode op) {457ir.Write(IROp::SetPCConst, 0, ir.AddConstant(GetCompilerPC()));458ir.Write(IROp::Break);459js.compiling = false;460}461462} // namespace Mipscomp463464465