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Path: blob/master/Core/MIPS/RiscV/RiscVCompBranch.cpp
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "Core/MIPS/RiscV/RiscVJit.h"18#include "Core/MIPS/RiscV/RiscVRegCache.h"1920// This file contains compilation for exits.21//22// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.23// Currently known non working ones should have DISABLE. No flags because that's in IR already.2425// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }26#define CONDITIONAL_DISABLE {}27#define DISABLE { CompIR_Generic(inst); return; }28#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }2930namespace MIPSComp {3132using namespace RiscVGen;33using namespace RiscVJitConstants;3435void RiscVJitBackend::CompIR_Exit(IRInst inst) {36CONDITIONAL_DISABLE;3738RiscVReg exitReg = INVALID_REG;39switch (inst.op) {40case IROp::ExitToConst:41FlushAll();42WriteConstExit(inst.constant);43break;4445case IROp::ExitToReg:46exitReg = regs_.MapGPR(inst.src1);47FlushAll();48// TODO: If ever we don't read this back in dispatcherPCInSCRATCH1_, we should zero upper.49MV(SCRATCH1, exitReg);50QuickJ(R_RA, dispatcherPCInSCRATCH1_);51break;5253case IROp::ExitToPC:54FlushAll();55QuickJ(R_RA, dispatcherCheckCoreState_);56break;5758default:59INVALIDOP;60break;61}62}6364void RiscVJitBackend::CompIR_ExitIf(IRInst inst) {65CONDITIONAL_DISABLE;6667RiscVReg lhs = INVALID_REG;68RiscVReg rhs = INVALID_REG;69FixupBranch fixup;70switch (inst.op) {71case IROp::ExitToConstIfEq:72case IROp::ExitToConstIfNeq:73regs_.Map(inst);74// We can't use SCRATCH1, which is destroyed by FlushAll()... but cheat and use R_RA.75NormalizeSrc12(inst, &lhs, &rhs, R_RA, SCRATCH2, true);76FlushAll();7778switch (inst.op) {79case IROp::ExitToConstIfEq:80fixup = BNE(lhs, rhs);81break;8283case IROp::ExitToConstIfNeq:84fixup = BEQ(lhs, rhs);85break;8687default:88INVALIDOP;89break;90}9192WriteConstExit(inst.constant);93SetJumpTarget(fixup);94break;9596case IROp::ExitToConstIfGtZ:97case IROp::ExitToConstIfGeZ:98case IROp::ExitToConstIfLtZ:99case IROp::ExitToConstIfLeZ:100regs_.Map(inst);101NormalizeSrc1(inst, &lhs, SCRATCH2, true);102FlushAll();103104switch (inst.op) {105case IROp::ExitToConstIfGtZ:106fixup = BGE(R_ZERO, lhs);107break;108109case IROp::ExitToConstIfGeZ:110fixup = BLT(lhs, R_ZERO);111break;112113case IROp::ExitToConstIfLtZ:114fixup = BGE(lhs, R_ZERO);115break;116117case IROp::ExitToConstIfLeZ:118fixup = BLT(R_ZERO, lhs);119break;120121default:122INVALIDOP;123break;124}125126WriteConstExit(inst.constant);127SetJumpTarget(fixup);128break;129130case IROp::ExitToConstIfFpTrue:131case IROp::ExitToConstIfFpFalse:132// Note: not used.133DISABLE;134break;135136default:137INVALIDOP;138break;139}140}141142} // namespace MIPSComp143144145