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Path: blob/master/Core/MIPS/RiscV/RiscVJit.h
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#pragma once1819#include <string>20#include <vector>21#include "Common/RiscVEmitter.h"22#include "Core/MIPS/IR/IRJit.h"23#include "Core/MIPS/IR/IRNativeCommon.h"24#include "Core/MIPS/JitCommon/JitState.h"25#include "Core/MIPS/JitCommon/JitCommon.h"26#include "Core/MIPS/RiscV/RiscVRegCache.h"2728namespace MIPSComp {2930class RiscVJitBackend : public RiscVGen::RiscVCodeBlock, public IRNativeBackend {31public:32RiscVJitBackend(JitOptions &jo, IRBlockCache &blocks);33~RiscVJitBackend();3435bool DescribeCodePtr(const u8 *ptr, std::string &name) const override;3637void GenerateFixedCode(MIPSState *mipsState) override;38bool CompileBlock(IRBlockCache *irBlockCache, int block_num, bool preload) override;39void ClearAllBlocks() override;40void InvalidateBlock(IRBlockCache *irBlockCache, int block_num) override;4142protected:43const CodeBlockCommon &CodeBlock() const override {44return *this;45}4647private:48void RestoreRoundingMode(bool force = false);49void ApplyRoundingMode(bool force = false);50void MovFromPC(RiscVGen::RiscVReg r);51void MovToPC(RiscVGen::RiscVReg r);52void WriteDebugPC(uint32_t pc);53void WriteDebugPC(RiscVGen::RiscVReg r);54void WriteDebugProfilerStatus(IRProfilerStatus status);5556void SaveStaticRegisters();57void LoadStaticRegisters();5859// Note: destroys SCRATCH1.60void FlushAll();6162void WriteConstExit(uint32_t pc);63void OverwriteExit(int srcOffset, int len, int block_num) override;6465void CompIR_Arith(IRInst inst) override;66void CompIR_Assign(IRInst inst) override;67void CompIR_Basic(IRInst inst) override;68void CompIR_Bits(IRInst inst) override;69void CompIR_Breakpoint(IRInst inst) override;70void CompIR_Compare(IRInst inst) override;71void CompIR_CondAssign(IRInst inst) override;72void CompIR_CondStore(IRInst inst) override;73void CompIR_Div(IRInst inst) override;74void CompIR_Exit(IRInst inst) override;75void CompIR_ExitIf(IRInst inst) override;76void CompIR_FArith(IRInst inst) override;77void CompIR_FAssign(IRInst inst) override;78void CompIR_FCompare(IRInst inst) override;79void CompIR_FCondAssign(IRInst inst) override;80void CompIR_FCvt(IRInst inst) override;81void CompIR_FLoad(IRInst inst) override;82void CompIR_FRound(IRInst inst) override;83void CompIR_FSat(IRInst inst) override;84void CompIR_FSpecial(IRInst inst) override;85void CompIR_FStore(IRInst inst) override;86void CompIR_Generic(IRInst inst) override;87void CompIR_HiLo(IRInst inst) override;88void CompIR_Interpret(IRInst inst) override;89void CompIR_Load(IRInst inst) override;90void CompIR_LoadShift(IRInst inst) override;91void CompIR_Logic(IRInst inst) override;92void CompIR_Mult(IRInst inst) override;93void CompIR_RoundingMode(IRInst inst) override;94void CompIR_Shift(IRInst inst) override;95void CompIR_Store(IRInst inst) override;96void CompIR_StoreShift(IRInst inst) override;97void CompIR_System(IRInst inst) override;98void CompIR_Transfer(IRInst inst) override;99void CompIR_VecArith(IRInst inst) override;100void CompIR_VecAssign(IRInst inst) override;101void CompIR_VecClamp(IRInst inst) override;102void CompIR_VecHoriz(IRInst inst) override;103void CompIR_VecLoad(IRInst inst) override;104void CompIR_VecPack(IRInst inst) override;105void CompIR_VecStore(IRInst inst) override;106void CompIR_ValidateAddress(IRInst inst) override;107108void SetScratch1ToSrc1Address(IRReg src1);109// Modifies SCRATCH regs.110int32_t AdjustForAddressOffset(RiscVGen::RiscVReg *reg, int32_t constant, int32_t range = 0);111void NormalizeSrc1(IRInst inst, RiscVGen::RiscVReg *reg, RiscVGen::RiscVReg tempReg, bool allowOverlap);112void NormalizeSrc12(IRInst inst, RiscVGen::RiscVReg *lhs, RiscVGen::RiscVReg *rhs, RiscVGen::RiscVReg lhsTempReg, RiscVGen::RiscVReg rhsTempReg, bool allowOverlap);113RiscVGen::RiscVReg NormalizeR(IRReg rs, IRReg rd, RiscVGen::RiscVReg tempReg);114115JitOptions &jo;116RiscVRegCache regs_;117118const u8 *outerLoop_ = nullptr;119const u8 *outerLoopPCInSCRATCH1_ = nullptr;120const u8 *dispatcherCheckCoreState_ = nullptr;121const u8 *dispatcherPCInSCRATCH1_ = nullptr;122const u8 *dispatcherNoCheck_ = nullptr;123const u8 *applyRoundingMode_ = nullptr;124125const u8 *saveStaticRegisters_ = nullptr;126const u8 *loadStaticRegisters_ = nullptr;127128int jitStartOffset_ = 0;129int compilingBlockNum_ = -1;130int logBlocks_ = 0;131};132133class RiscVJit : public IRNativeJit {134public:135RiscVJit(MIPSState *mipsState)136: IRNativeJit(mipsState), rvBackend_(jo, blocks_) {137Init(rvBackend_);138}139140private:141RiscVJitBackend rvBackend_;142};143144} // namespace MIPSComp145146147