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Path: blob/master/Core/MIPS/RiscV/RiscVRegCache.cpp
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#ifndef offsetof18#include <cstddef>19#endif2021#include "Common/CPUDetect.h"22#include "Core/MIPS/IR/IRInst.h"23#include "Core/MIPS/IR/IRAnalysis.h"24#include "Core/MIPS/RiscV/RiscVRegCache.h"25#include "Core/MIPS/JitCommon/JitState.h"26#include "Core/Reporting.h"2728using namespace RiscVGen;29using namespace RiscVJitConstants;3031RiscVRegCache::RiscVRegCache(MIPSComp::JitOptions *jo)32: IRNativeRegCacheBase(jo) {33// TODO: Update these when using RISC-V V.34config_.totalNativeRegs = NUM_RVGPR + NUM_RVFPR;35config_.mapUseVRegs = false;36config_.mapFPUSIMD = false;37}3839void RiscVRegCache::Init(RiscVEmitter *emitter) {40emit_ = emitter;41}4243void RiscVRegCache::SetupInitialRegs() {44IRNativeRegCacheBase::SetupInitialRegs();4546// Treat R_ZERO a bit specially, but it's basically static alloc too.47nrInitial_[R_ZERO].mipsReg = MIPS_REG_ZERO;48nrInitial_[R_ZERO].normalized32 = true;4950// Since we also have a fixed zero, mark it as a static allocation.51mrInitial_[MIPS_REG_ZERO].loc = MIPSLoc::REG_IMM;52mrInitial_[MIPS_REG_ZERO].nReg = R_ZERO;53mrInitial_[MIPS_REG_ZERO].imm = 0;54mrInitial_[MIPS_REG_ZERO].isStatic = true;55}5657const int *RiscVRegCache::GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const {58base = X0;5960if (type == MIPSLoc::REG) {61// X8 and X9 are the most ideal for static alloc because they can be used with compression.62// Otherwise we stick to saved regs - might not be necessary.63static const int allocationOrder[] = {64X8, X9, X12, X13, X14, X15, X5, X6, X7, X16, X17, X18, X19, X20, X21, X22, X23, X28, X29, X30, X31,65};66static const int allocationOrderStaticAlloc[] = {67X12, X13, X14, X15, X5, X6, X7, X16, X17, X21, X22, X23, X28, X29, X30, X31,68};6970if (jo_->useStaticAlloc) {71count = ARRAY_SIZE(allocationOrderStaticAlloc);72return allocationOrderStaticAlloc;73} else {74count = ARRAY_SIZE(allocationOrder);75return allocationOrder;76}77} else if (type == MIPSLoc::FREG) {78// F8 through F15 are used for compression, so they are great.79static const int allocationOrder[] = {80F8, F9, F10, F11, F12, F13, F14, F15,81F0, F1, F2, F3, F4, F5, F6, F7,82F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,83};8485count = ARRAY_SIZE(allocationOrder);86return allocationOrder;87} else {88_assert_msg_(false, "Allocation order not yet implemented");89count = 0;90return nullptr;91}92}9394const RiscVRegCache::StaticAllocation *RiscVRegCache::GetStaticAllocations(int &count) const {95static const StaticAllocation allocs[] = {96{ MIPS_REG_SP, X8, MIPSLoc::REG, true },97{ MIPS_REG_V0, X9, MIPSLoc::REG },98{ MIPS_REG_V1, X18, MIPSLoc::REG },99{ MIPS_REG_A0, X19, MIPSLoc::REG },100{ MIPS_REG_RA, X20, MIPSLoc::REG },101};102103if (jo_->useStaticAlloc) {104count = ARRAY_SIZE(allocs);105return allocs;106}107return IRNativeRegCacheBase::GetStaticAllocations(count);108}109110void RiscVRegCache::EmitLoadStaticRegisters() {111int count;112const StaticAllocation *allocs = GetStaticAllocations(count);113for (int i = 0; i < count; i++) {114int offset = GetMipsRegOffset(allocs[i].mr);115if (allocs[i].pointerified && jo_->enablePointerify) {116emit_->LWU((RiscVReg)allocs[i].nr, CTXREG, offset);117emit_->ADD((RiscVReg)allocs[i].nr, (RiscVReg)allocs[i].nr, MEMBASEREG);118} else {119emit_->LW((RiscVReg)allocs[i].nr, CTXREG, offset);120}121}122}123124void RiscVRegCache::EmitSaveStaticRegisters() {125int count;126const StaticAllocation *allocs = GetStaticAllocations(count);127// This only needs to run once (by Asm) so checks don't need to be fast.128for (int i = 0; i < count; i++) {129int offset = GetMipsRegOffset(allocs[i].mr);130emit_->SW((RiscVReg)allocs[i].nr, CTXREG, offset);131}132}133134void RiscVRegCache::FlushBeforeCall() {135// These registers are not preserved by function calls.136// They match between X0 and F0, conveniently.137for (int i = 5; i <= 7; ++i) {138FlushNativeReg(X0 + i);139FlushNativeReg(F0 + i);140}141for (int i = 10; i <= 17; ++i) {142FlushNativeReg(X0 + i);143FlushNativeReg(F0 + i);144}145for (int i = 28; i <= 31; ++i) {146FlushNativeReg(X0 + i);147FlushNativeReg(F0 + i);148}149}150151bool RiscVRegCache::IsNormalized32(IRReg mipsReg) {152_dbg_assert_(IsValidGPR(mipsReg));153if (XLEN == 32)154return true;155if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) {156return nr[mr[mipsReg].nReg].normalized32;157}158return false;159}160161RiscVGen::RiscVReg RiscVRegCache::Normalize32(IRReg mipsReg, RiscVGen::RiscVReg destReg) {162_dbg_assert_(IsValidGPR(mipsReg));163_dbg_assert_(destReg == INVALID_REG || (destReg > X0 && destReg <= X31));164165RiscVReg reg = (RiscVReg)mr[mipsReg].nReg;166if (XLEN == 32)167return reg;168169switch (mr[mipsReg].loc) {170case MIPSLoc::IMM:171case MIPSLoc::MEM:172_assert_msg_(false, "Cannot normalize an imm or mem");173return INVALID_REG;174175case MIPSLoc::REG:176case MIPSLoc::REG_IMM:177if (!nr[mr[mipsReg].nReg].normalized32) {178if (destReg == INVALID_REG) {179emit_->SEXT_W((RiscVReg)mr[mipsReg].nReg, (RiscVReg)mr[mipsReg].nReg);180nr[mr[mipsReg].nReg].normalized32 = true;181nr[mr[mipsReg].nReg].pointerified = false;182} else {183emit_->SEXT_W(destReg, (RiscVReg)mr[mipsReg].nReg);184}185} else if (destReg != INVALID_REG) {186emit_->SEXT_W(destReg, (RiscVReg)mr[mipsReg].nReg);187}188break;189190case MIPSLoc::REG_AS_PTR:191_dbg_assert_(nr[mr[mipsReg].nReg].normalized32 == false);192if (destReg == INVALID_REG) {193// If we can pointerify, SEXT_W will be enough.194if (!jo_->enablePointerify)195AdjustNativeRegAsPtr(mr[mipsReg].nReg, false);196emit_->SEXT_W((RiscVReg)mr[mipsReg].nReg, (RiscVReg)mr[mipsReg].nReg);197mr[mipsReg].loc = MIPSLoc::REG;198nr[mr[mipsReg].nReg].normalized32 = true;199nr[mr[mipsReg].nReg].pointerified = false;200} else if (!jo_->enablePointerify) {201emit_->SUB(destReg, (RiscVReg)mr[mipsReg].nReg, MEMBASEREG);202emit_->SEXT_W(destReg, destReg);203} else {204emit_->SEXT_W(destReg, (RiscVReg)mr[mipsReg].nReg);205}206break;207208default:209_assert_msg_(false, "Should not normalize32 floats");210break;211}212213return destReg == INVALID_REG ? reg : destReg;214}215216RiscVReg RiscVRegCache::TryMapTempImm(IRReg r) {217_dbg_assert_(IsValidGPR(r));218// If already mapped, no need for a temporary.219if (IsGPRMapped(r)) {220return R(r);221}222223if (mr[r].loc == MIPSLoc::IMM) {224if (mr[r].imm == 0) {225return R_ZERO;226}227228// Try our luck - check for an exact match in another rvreg.229for (int i = 0; i < TOTAL_MAPPABLE_IRREGS; ++i) {230if (mr[i].loc == MIPSLoc::REG_IMM && mr[i].imm == mr[r].imm) {231// Awesome, let's just use this reg.232return (RiscVReg)mr[i].nReg;233}234}235}236237return INVALID_REG;238}239240RiscVReg RiscVRegCache::GetAndLockTempGPR() {241RiscVReg reg = (RiscVReg)AllocateReg(MIPSLoc::REG, MIPSMap::INIT);242if (reg != INVALID_REG) {243nr[reg].tempLockIRIndex = irIndex_;244}245return reg;246}247248RiscVReg RiscVRegCache::MapWithFPRTemp(const IRInst &inst) {249return (RiscVReg)MapWithTemp(inst, MIPSLoc::FREG);250}251252RiscVReg RiscVRegCache::MapGPR(IRReg mipsReg, MIPSMap mapFlags) {253_dbg_assert_(IsValidGPR(mipsReg));254255// Okay, not mapped, so we need to allocate an RV register.256IRNativeReg nreg = MapNativeReg(MIPSLoc::REG, mipsReg, 1, mapFlags);257return (RiscVReg)nreg;258}259260RiscVReg RiscVRegCache::MapGPRAsPointer(IRReg reg) {261return (RiscVReg)MapNativeRegAsPointer(reg);262}263264RiscVReg RiscVRegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) {265_dbg_assert_(IsValidFPR(mipsReg));266_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);267268IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, mipsReg + 32, 1, mapFlags);269if (nreg != -1)270return (RiscVReg)nreg;271return INVALID_REG;272}273274void RiscVRegCache::AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) {275RiscVReg r = (RiscVReg)(X0 + nreg);276_assert_(r >= X0 && r <= X31);277if (state) {278#ifdef MASKED_PSP_MEMORY279// This destroys the value...280_dbg_assert_(!nr[nreg].isDirty);281emit_->SLLIW(r, r, 2);282emit_->SRLIW(r, r, 2);283emit_->ADD(r, r, MEMBASEREG);284#else285// Clear the top bits to be safe.286if (cpu_info.RiscV_Zba) {287emit_->ADD_UW(r, r, MEMBASEREG);288} else {289_assert_(XLEN == 64);290emit_->SLLI(r, r, 32);291emit_->SRLI(r, r, 32);292emit_->ADD(r, r, MEMBASEREG);293}294#endif295nr[nreg].normalized32 = false;296} else {297#ifdef MASKED_PSP_MEMORY298_dbg_assert_(!nr[nreg].isDirty);299#endif300emit_->SUB(r, r, MEMBASEREG);301nr[nreg].normalized32 = false;302}303}304305bool RiscVRegCache::IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) {306// No special flags except VREG, skip the check for a little speed.307if (type != MIPSLoc::VREG)308return true;309return IRNativeRegCacheBase::IsNativeRegCompatible(nreg, type, flags, lanes);310}311312void RiscVRegCache::LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) {313RiscVReg r = (RiscVReg)(X0 + nreg);314_dbg_assert_(r > X0);315_dbg_assert_(first != MIPS_REG_ZERO);316if (r <= X31) {317_assert_(lanes == 1 || (lanes == 2 && first == IRREG_LO));318if (lanes == 1)319emit_->LW(r, CTXREG, GetMipsRegOffset(first));320else if (lanes == 2)321emit_->LD(r, CTXREG, GetMipsRegOffset(first));322else323_assert_(false);324nr[nreg].normalized32 = true;325} else {326_dbg_assert_(r >= F0 && r <= F31);327// Multilane not yet supported.328_assert_(lanes == 1);329if (mr[first].loc == MIPSLoc::FREG) {330emit_->FL(32, r, CTXREG, GetMipsRegOffset(first));331} else {332_assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot store this type: %d", (int)mr[first].loc);333}334}335}336337void RiscVRegCache::StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) {338RiscVReg r = (RiscVReg)(X0 + nreg);339_dbg_assert_(r > X0);340_dbg_assert_(first != MIPS_REG_ZERO);341if (r <= X31) {342// Multilane not yet supported.343_assert_(lanes == 1 || (lanes == 2 && first == IRREG_LO));344_assert_(mr[first].loc == MIPSLoc::REG || mr[first].loc == MIPSLoc::REG_IMM);345if (lanes == 1)346emit_->SW(r, CTXREG, GetMipsRegOffset(first));347else if (lanes == 2)348emit_->SD(r, CTXREG, GetMipsRegOffset(first));349else350_assert_(false);351} else {352_dbg_assert_(r >= F0 && r <= F31);353// Multilane not yet supported.354_assert_(lanes == 1);355if (mr[first].loc == MIPSLoc::FREG) {356emit_->FS(32, r, CTXREG, GetMipsRegOffset(first));357} else {358_assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot store this type: %d", (int)mr[first].loc);359}360}361}362363void RiscVRegCache::SetNativeRegValue(IRNativeReg nreg, uint32_t imm) {364RiscVReg r = (RiscVReg)(X0 + nreg);365if (r == R_ZERO && imm == 0)366return;367_dbg_assert_(r > X0 && r <= X31);368emit_->LI(r, (int32_t)imm);369370// We always use 32-bit immediates, so this is normalized now.371nr[nreg].normalized32 = true;372}373374void RiscVRegCache::StoreRegValue(IRReg mreg, uint32_t imm) {375_assert_(IsValidGPRNoZero(mreg));376// Try to optimize using a different reg.377RiscVReg storeReg = INVALID_REG;378379// Zero is super easy.380if (imm == 0) {381storeReg = R_ZERO;382} else {383// Could we get lucky? Check for an exact match in another rvreg.384for (int i = 0; i < TOTAL_MAPPABLE_IRREGS; ++i) {385if (mr[i].loc == MIPSLoc::REG_IMM && mr[i].imm == imm) {386// Awesome, let's just store this reg.387storeReg = (RiscVReg)mr[i].nReg;388break;389}390}391392if (storeReg == INVALID_REG) {393emit_->LI(SCRATCH1, imm);394storeReg = SCRATCH1;395}396}397398emit_->SW(storeReg, CTXREG, GetMipsRegOffset(mreg));399}400401RiscVReg RiscVRegCache::R(IRReg mipsReg) {402_dbg_assert_(IsValidGPR(mipsReg));403_dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM);404if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) {405return (RiscVReg)mr[mipsReg].nReg;406} else {407ERROR_LOG_REPORT(Log::JIT, "Reg %i not in riscv reg", mipsReg);408return INVALID_REG; // BAAAD409}410}411412RiscVReg RiscVRegCache::RPtr(IRReg mipsReg) {413_dbg_assert_(IsValidGPR(mipsReg));414_dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM || mr[mipsReg].loc == MIPSLoc::REG_AS_PTR);415if (mr[mipsReg].loc == MIPSLoc::REG_AS_PTR) {416return (RiscVReg)mr[mipsReg].nReg;417} else if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) {418int rv = mr[mipsReg].nReg;419_dbg_assert_(nr[rv].pointerified);420if (nr[rv].pointerified) {421return (RiscVReg)mr[mipsReg].nReg;422} else {423ERROR_LOG(Log::JIT, "Tried to use a non-pointer register as a pointer");424return INVALID_REG;425}426} else {427ERROR_LOG_REPORT(Log::JIT, "Reg %i not in riscv reg", mipsReg);428return INVALID_REG; // BAAAD429}430}431432RiscVReg RiscVRegCache::F(IRReg mipsReg) {433_dbg_assert_(IsValidFPR(mipsReg));434_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::FREG);435if (mr[mipsReg + 32].loc == MIPSLoc::FREG) {436return (RiscVReg)mr[mipsReg + 32].nReg;437} else {438ERROR_LOG_REPORT(Log::JIT, "Reg %i not in riscv reg", mipsReg);439return INVALID_REG; // BAAAD440}441}442443444