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Path: blob/master/Core/MIPS/RiscV/RiscVRegCache.h
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#pragma once1819#include "Common/RiscVEmitter.h"20#include "Core/MIPS/MIPS.h"21#include "Core/MIPS/IR/IRJit.h"22#include "Core/MIPS/IR/IRRegCache.h"2324namespace RiscVJitConstants {2526// Note: we don't support 32-bit or 128-bit CPUs currently.27constexpr int XLEN = 64;2829const RiscVGen::RiscVReg DOWNCOUNTREG = RiscVGen::X24;30const RiscVGen::RiscVReg JITBASEREG = RiscVGen::X25;31const RiscVGen::RiscVReg CTXREG = RiscVGen::X26;32const RiscVGen::RiscVReg MEMBASEREG = RiscVGen::X27;33// TODO: Experiment. X7-X13 are compressed regs. X8/X9 are saved so nice for static alloc, though.34const RiscVGen::RiscVReg SCRATCH1 = RiscVGen::X10;35const RiscVGen::RiscVReg SCRATCH2 = RiscVGen::X11;3637} // namespace RiscVJitConstants3839class RiscVRegCache : public IRNativeRegCacheBase {40public:41RiscVRegCache(MIPSComp::JitOptions *jo);4243void Init(RiscVGen::RiscVEmitter *emitter);4445// May fail and return INVALID_REG if it needs flushing.46RiscVGen::RiscVReg TryMapTempImm(IRReg reg);4748// Returns an RV register containing the requested MIPS register.49RiscVGen::RiscVReg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);50RiscVGen::RiscVReg MapGPRAsPointer(IRReg reg);51RiscVGen::RiscVReg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);5253RiscVGen::RiscVReg MapWithFPRTemp(const IRInst &inst);5455bool IsNormalized32(IRReg reg);5657// Copies to another reg if specified, otherwise same reg.58RiscVGen::RiscVReg Normalize32(IRReg reg, RiscVGen::RiscVReg destReg = RiscVGen::INVALID_REG);5960void FlushBeforeCall();6162RiscVGen::RiscVReg GetAndLockTempGPR();6364RiscVGen::RiscVReg R(IRReg preg); // Returns a cached register, while checking that it's NOT mapped as a pointer65RiscVGen::RiscVReg RPtr(IRReg preg); // Returns a cached register, if it has been mapped as a pointer66RiscVGen::RiscVReg F(IRReg preg);6768// These are called once on startup to generate functions, that you should then call.69void EmitLoadStaticRegisters();70void EmitSaveStaticRegisters();7172protected:73void SetupInitialRegs() override;74const StaticAllocation *GetStaticAllocations(int &count) const override;75const int *GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const override;76void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override;7778bool IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) override;79void LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;80void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;81void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override;82void StoreRegValue(IRReg mreg, uint32_t imm) override;8384private:85RiscVGen::RiscVEmitter *emit_ = nullptr;8687enum {88NUM_RVGPR = 32,89NUM_RVFPR = 32,90NUM_RVVPR = 32,91};92};939495