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Path: blob/master/Core/MIPS/x86/CompBranch.cpp
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// Copyright (c) 2012- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "ppsspp_config.h"18#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)1920#include "Common/Data/Convert/SmallDataConvert.h"21#include "Common/Profiler/Profiler.h"2223#include "Core/Config.h"24#include "Core/Core.h"25#include "Core/Reporting.h"26#include "Core/HLE/HLE.h"27#include "Core/HLE/HLETables.h"28#include "Core/MemMap.h"2930#include "Core/MIPS/MIPS.h"31#include "Core/MIPS/MIPSCodeUtils.h"32#include "Core/MIPS/MIPSAnalyst.h"33#include "Core/MIPS/MIPSTables.h"3435#include "Core/MIPS/x86/Jit.h"36#include "Core/MIPS/x86/RegCache.h"37#include "Core/MIPS/JitCommon/JitBlockCache.h"3839#define _RS MIPS_GET_RS(op)40#define _RT MIPS_GET_RT(op)41#define _RD MIPS_GET_RD(op)42#define _FS MIPS_GET_FS(op)43#define _FT MIPS_GET_FT(op)44#define _FD MIPS_GET_FD(op)45#define _SA MIPS_GET_SA(op)46#define _POS ((op>> 6) & 0x1F)47#define _SIZE ((op>>11) & 0x1F)48#define _IMM26 (op & 0x03FFFFFF)49#define TARGET16 ((int)(SignExtend16ToU32(op) << 2))50#define TARGET26 (_IMM26 << 2)5152#define LOOPOPTIMIZATION 05354using namespace MIPSAnalyst;5556// NOTE: Can't use CONDITIONAL_DISABLE in this file, branches are so special57// that they cannot be interpreted in the context of the Jit.5859// But we can at least log and compare.60// #define DO_CONDITIONAL_LOG 161#define DO_CONDITIONAL_LOG 06263// We can also disable nice delay slots.64// #define CONDITIONAL_NICE_DELAYSLOT branchInfo.delaySlotIsNice = false;65#define CONDITIONAL_NICE_DELAYSLOT ;6667#if DO_CONDITIONAL_LOG68#define CONDITIONAL_LOG BranchLog(op);69#define CONDITIONAL_LOG_EXIT(addr) BranchLogExit(op, addr, false);70#define CONDITIONAL_LOG_EXIT_EAX() BranchLogExit(op, 0, true);71#else72#define CONDITIONAL_LOG ;73#define CONDITIONAL_LOG_EXIT(addr) ;74#define CONDITIONAL_LOG_EXIT_EAX() ;75#endif7677namespace MIPSComp78{79using namespace Gen;8081static void JitBranchLog(MIPSOpcode op, u32 pc) {82currentMIPS->pc = pc;83currentMIPS->inDelaySlot = false;8485MIPSInterpretFunc func = MIPSGetInterpretFunc(op);86MIPSInfo info = MIPSGetInfo(op);87func(op);8889// Branch taken, use nextPC.90if (currentMIPS->inDelaySlot)91currentMIPS->intBranchExit = currentMIPS->nextPC;92else93{94// Branch not taken, likely delay slot skipped.95if (info & LIKELY)96currentMIPS->intBranchExit = currentMIPS->pc;97// Branch not taken, so increment over delay slot.98else99currentMIPS->intBranchExit = currentMIPS->pc + 4;100}101102currentMIPS->pc = pc;103currentMIPS->inDelaySlot = false;104}105106static void JitBranchLogMismatch(MIPSOpcode op, u32 pc)107{108char temp[256];109MIPSDisAsm(op, pc, temp, sizeof(temp), true);110ERROR_LOG(Log::JIT, "Bad jump: %s - int:%08x jit:%08x", temp, currentMIPS->intBranchExit, currentMIPS->jitBranchExit);111Core_EnableStepping(true, "jit.branchdebug", pc);112}113114void Jit::BranchLog(MIPSOpcode op)115{116FlushAll();117ABI_CallFunctionCC(thunks.ProtectFunction(&JitBranchLog), op.encoding, GetCompilerPC());118}119120void Jit::BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX)121{122OpArg destArg = useEAX ? R(EAX) : Imm32(dest);123124CMP(32, MIPSSTATE_VAR(intBranchExit), destArg);125FixupBranch skip = J_CC(CC_E);126127MOV(32, MIPSSTATE_VAR(jitBranchExit), destArg);128ABI_CallFunctionCC(thunks.ProtectFunction(&JitBranchLogMismatch), op.encoding, GetCompilerPC());129// Restore EAX, we probably ruined it.130if (useEAX)131MOV(32, R(EAX), MIPSSTATE_VAR(jitBranchExit));132133SetJumpTarget(skip);134}135136CCFlags Jit::FlipCCFlag(CCFlags flag)137{138switch (flag)139{140case CC_O: return CC_NO;141case CC_NO: return CC_O;142case CC_B: return CC_NB;143case CC_NB: return CC_B;144case CC_Z: return CC_NZ;145case CC_NZ: return CC_Z;146case CC_BE: return CC_NBE;147case CC_NBE: return CC_BE;148case CC_S: return CC_NS;149case CC_NS: return CC_S;150case CC_P: return CC_NP;151case CC_NP: return CC_P;152case CC_L: return CC_NL;153case CC_NL: return CC_L;154case CC_LE: return CC_NLE;155case CC_NLE: return CC_LE;156}157ERROR_LOG_REPORT(Log::JIT, "FlipCCFlag: Unexpected CC flag: %d", flag);158return CC_O;159}160161CCFlags Jit::SwapCCFlag(CCFlags flag)162{163// This swaps the comparison for an lhs/rhs swap, but doesn't flip/invert the logic.164switch (flag)165{166case CC_O: return CC_O;167case CC_NO: return CC_NO;168case CC_B: return CC_A;169case CC_NB: return CC_NA;170case CC_Z: return CC_Z;171case CC_NZ: return CC_NZ;172case CC_BE: return CC_AE;173case CC_NBE: return CC_NAE;174case CC_S: return CC_S;175case CC_NS: return CC_NS;176case CC_P: return CC_P;177case CC_NP: return CC_NP;178case CC_L: return CC_G;179case CC_NL: return CC_NG;180case CC_LE: return CC_GE;181case CC_NLE: return CC_NGE;182}183ERROR_LOG_REPORT(Log::JIT, "SwapCCFlag: Unexpected CC flag: %d", flag);184return CC_O;185}186187bool Jit::PredictTakeBranch(u32 targetAddr, bool likely) {188// If it's likely, it's... probably likely, right?189if (likely)190return true;191192// TODO: Normal branch prediction would be to take branches going upward to lower addresses.193// However, this results in worse performance as of this comment's writing.194// The reverse check generally gives better or same performance.195return targetAddr > GetCompilerPC();196}197198void Jit::CompBranchExits(CCFlags cc, u32 targetAddr, u32 notTakenAddr, const BranchInfo &branchInfo) {199if (branchInfo.andLink)200gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);201202// We may want to try to continue along this branch a little while, to reduce reg flushing.203bool predictTakeBranch = PredictTakeBranch(targetAddr, branchInfo.likely);204if (!branchInfo.delaySlotIsBranch && CanContinueBranch(predictTakeBranch ? targetAddr : notTakenAddr))205{206if (predictTakeBranch)207cc = FlipCCFlag(cc);208209Gen::FixupBranch ptr;210RegCacheState state;211if (!branchInfo.likely)212{213if (!branchInfo.delaySlotIsNice)214CompileDelaySlot(DELAYSLOT_SAFE);215ptr = J_CC(cc, true);216GetStateAndFlushAll(state);217}218else219{220ptr = J_CC(cc, true);221if (predictTakeBranch)222GetStateAndFlushAll(state);223else224{225// We need to get the state BEFORE the delay slot is compiled.226gpr.GetState(state.gpr);227fpr.GetState(state.fpr);228CompileDelaySlot(DELAYSLOT_FLUSH);229}230}231232if (predictTakeBranch)233{234// We flipped the cc, the not taken case is first.235CONDITIONAL_LOG_EXIT(notTakenAddr);236WriteExit(notTakenAddr, js.nextExit++);237238// Now our taken path. Bring the regs back, we didn't flush 'em after all.239SetJumpTarget(ptr);240RestoreState(state);241CONDITIONAL_LOG_EXIT(targetAddr);242243// Don't forget to run the delay slot if likely.244if (branchInfo.likely)245CompileDelaySlot(DELAYSLOT_NICE);246247AddContinuedBlock(targetAddr);248// Account for the increment in the loop.249js.compilerPC = targetAddr - 4;250// In case the delay slot was a break or something.251js.compiling = true;252}253else254{255// Take the branch256CONDITIONAL_LOG_EXIT(targetAddr);257WriteExit(targetAddr, js.nextExit++);258259// Not taken260SetJumpTarget(ptr);261RestoreState(state);262CONDITIONAL_LOG_EXIT(notTakenAddr);263264// Account for the delay slot.265js.compilerPC += 4;266// In case the delay slot was a break or something.267js.compiling = true;268}269}270else271{272Gen::FixupBranch ptr;273if (!branchInfo.likely)274{275if (!branchInfo.delaySlotIsNice && !branchInfo.delaySlotIsBranch)276CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);277else278FlushAll();279ptr = J_CC(cc, true);280}281else282{283FlushAll();284ptr = J_CC(cc, true);285if (!branchInfo.delaySlotIsBranch)286CompileDelaySlot(DELAYSLOT_FLUSH);287}288289// Handle the linkage of a delay slot, even when we're taking the branch.290if (branchInfo.delaySlotIsBranch) {291// We still link when the branch is taken (targetAddr case.)292// Remember, it's from the perspective of the delay slot, so +12.293if ((branchInfo.delaySlotInfo & OUT_RA) != 0)294gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 12);295if ((branchInfo.delaySlotInfo & OUT_RD) != 0)296gpr.SetImm(MIPS_GET_RD(branchInfo.delaySlotOp), GetCompilerPC() + 12);297FlushAll();298}299300// Take the branch301CONDITIONAL_LOG_EXIT(targetAddr);302WriteExit(targetAddr, js.nextExit++);303304// Not taken305SetJumpTarget(ptr);306CONDITIONAL_LOG_EXIT(notTakenAddr);307WriteExit(notTakenAddr, js.nextExit++);308js.compiling = false;309}310}311312void Jit::CompBranchExit(bool taken, u32 targetAddr, u32 notTakenAddr, const BranchInfo &branchInfo) {313// Continuing is handled in the imm branch case... TODO: move it here?314if (branchInfo.andLink)315gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);316if (branchInfo.delaySlotIsBranch) {317if (taken) {318// We still link when the branch is taken (targetAddr case.)319// Remember, it's from the perspective of the delay slot, so +12.320if ((branchInfo.delaySlotInfo & OUT_RA) != 0)321gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 12);322if ((branchInfo.delaySlotInfo & OUT_RD) != 0)323gpr.SetImm(MIPS_GET_RD(branchInfo.delaySlotOp), GetCompilerPC() + 12);324}325FlushAll();326} else if (taken || !branchInfo.likely) {327CompileDelaySlot(DELAYSLOT_FLUSH);328} else {329FlushAll();330}331332const u32 destAddr = taken ? targetAddr : notTakenAddr;333CONDITIONAL_LOG_EXIT(destAddr);334WriteExit(destAddr, js.nextExit++);335js.compiling = false;336}337338void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)339{340CONDITIONAL_LOG;341if (js.inDelaySlot) {342ERROR_LOG_REPORT(Log::JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);343return;344}345int offset = TARGET16;346MIPSGPReg rt = _RT;347MIPSGPReg rs = _RS;348u32 targetAddr = GetCompilerPC() + offset + 4;349350BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), false, likely);351branchInfo.delaySlotIsNice = IsDelaySlotNiceReg(op, branchInfo.delaySlotOp, rt, rs);352CONDITIONAL_NICE_DELAYSLOT;353354bool immBranch = false;355bool immBranchTaken = false;356if (gpr.IsImm(rs) && gpr.IsImm(rt) && !branchInfo.delaySlotIsBranch) {357// The cc flags are opposites: when NOT to take the branch.358bool immBranchNotTaken;359s32 rsImm = (s32)gpr.GetImm(rs);360s32 rtImm = (s32)gpr.GetImm(rt);361362switch (cc)363{364case CC_E: immBranchNotTaken = rsImm == rtImm; break;365case CC_NE: immBranchNotTaken = rsImm != rtImm; break;366default: immBranchNotTaken = false; _dbg_assert_msg_(false, "Bad cc flag in BranchRSRTComp().");367}368immBranch = true;369immBranchTaken = !immBranchNotTaken;370}371372if (jo.immBranches && immBranch && js.numInstructions < jo.continueMaxInstructions)373{374if (!immBranchTaken)375{376// Skip the delay slot if likely, otherwise it'll be the next instruction.377if (likely)378js.compilerPC += 4;379return;380}381382// Branch taken. Always compile the delay slot, and then go to dest.383CompileDelaySlot(DELAYSLOT_NICE);384AddContinuedBlock(targetAddr);385// Account for the increment in the loop.386js.compilerPC = targetAddr - 4;387// In case the delay slot was a break or something.388js.compiling = true;389return;390}391392js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);393394u32 notTakenTarget = ResolveNotTakenTarget(branchInfo);395if (immBranch)396CompBranchExit(immBranchTaken, targetAddr, notTakenTarget, branchInfo);397else398{399if (!likely && branchInfo.delaySlotIsNice && !branchInfo.delaySlotIsBranch)400CompileDelaySlot(DELAYSLOT_NICE);401402if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)403{404gpr.KillImmediate(rs, true, false);405CMP(32, gpr.R(rs), Imm32(0));406}407else408{409gpr.MapReg(rs, true, false);410CMP(32, gpr.R(rs), gpr.R(rt));411}412413CompBranchExits(cc, targetAddr, notTakenTarget, branchInfo);414}415}416417void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely)418{419CONDITIONAL_LOG;420if (js.inDelaySlot) {421ERROR_LOG_REPORT(Log::JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);422return;423}424int offset = TARGET16;425MIPSGPReg rs = _RS;426u32 targetAddr = GetCompilerPC() + offset + 4;427428BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), andLink, likely);429branchInfo.delaySlotIsNice = IsDelaySlotNiceReg(op, branchInfo.delaySlotOp, rs);430js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);431CONDITIONAL_NICE_DELAYSLOT;432433bool immBranch = false;434bool immBranchTaken = false;435if (gpr.IsImm(rs) && !branchInfo.delaySlotIsBranch) {436// The cc flags are opposites: when NOT to take the branch.437bool immBranchNotTaken;438s32 imm = (s32)gpr.GetImm(rs);439440switch (cc)441{442case CC_G: immBranchNotTaken = imm > 0; break;443case CC_GE: immBranchNotTaken = imm >= 0; break;444case CC_L: immBranchNotTaken = imm < 0; break;445case CC_LE: immBranchNotTaken = imm <= 0; break;446default: immBranchNotTaken = false; _dbg_assert_msg_(false, "Bad cc flag in BranchRSZeroComp().");447}448immBranch = true;449immBranchTaken = !immBranchNotTaken;450}451452if (jo.immBranches && immBranch && js.numInstructions < jo.continueMaxInstructions)453{454if (!immBranchTaken)455{456// Skip the delay slot if likely, otherwise it'll be the next instruction.457if (andLink)458gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);459if (likely)460js.compilerPC += 4;461return;462}463464// Branch taken. Always compile the delay slot, and then go to dest.465if (andLink)466gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);467CompileDelaySlot(DELAYSLOT_NICE);468469AddContinuedBlock(targetAddr);470// Account for the increment in the loop.471js.compilerPC = targetAddr - 4;472// In case the delay slot was a break or something.473js.compiling = true;474return;475}476477js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);478479u32 notTakenTarget = ResolveNotTakenTarget(branchInfo);480if (immBranch)481CompBranchExit(immBranchTaken, targetAddr, notTakenTarget, branchInfo);482else483{484if (!likely && branchInfo.delaySlotIsNice && !branchInfo.delaySlotIsBranch)485CompileDelaySlot(DELAYSLOT_NICE);486487gpr.MapReg(rs, true, false);488CMP(32, gpr.R(rs), Imm32(0));489490CompBranchExits(cc, targetAddr, notTakenTarget, branchInfo);491}492}493494495void Jit::Comp_RelBranch(MIPSOpcode op)496{497switch (op>>26)498{499case 4: BranchRSRTComp(op, CC_NZ, false); break;//beq500case 5: BranchRSRTComp(op, CC_Z, false); break;//bne501502case 6: BranchRSZeroComp(op, CC_G, false, false); break;//blez503case 7: BranchRSZeroComp(op, CC_LE, false, false); break;//bgtz504505case 20: BranchRSRTComp(op, CC_NZ, true); break;//beql506case 21: BranchRSRTComp(op, CC_Z, true); break;//bnel507508case 22: BranchRSZeroComp(op, CC_G, false, true); break;//blezl509case 23: BranchRSZeroComp(op, CC_LE, false, true); break;//bgtzl510511default:512_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");513break;514}515}516517void Jit::Comp_RelBranchRI(MIPSOpcode op)518{519switch ((op >> 16) & 0x1F)520{521case 0: BranchRSZeroComp(op, CC_GE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz522case 1: BranchRSZeroComp(op, CC_L, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez523case 2: BranchRSZeroComp(op, CC_GE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl524case 3: BranchRSZeroComp(op, CC_L, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl525case 16: BranchRSZeroComp(op, CC_GE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal526case 17: BranchRSZeroComp(op, CC_L, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal527case 18: BranchRSZeroComp(op, CC_GE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall528case 19: BranchRSZeroComp(op, CC_L, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall529default:530_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");531break;532}533}534535536// If likely is set, discard the branch slot if NOT taken.537void Jit::BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)538{539CONDITIONAL_LOG;540if (js.inDelaySlot) {541ERROR_LOG_REPORT(Log::JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);542return;543}544int offset = TARGET16;545u32 targetAddr = GetCompilerPC() + offset + 4;546547BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), false, likely);548branchInfo.delaySlotIsNice = IsDelaySlotNiceFPU(op, branchInfo.delaySlotOp);549CONDITIONAL_NICE_DELAYSLOT;550551js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);552if (!likely && branchInfo.delaySlotIsNice && !branchInfo.delaySlotIsBranch)553CompileDelaySlot(DELAYSLOT_NICE);554555gpr.KillImmediate(MIPS_REG_FPCOND, true, false);556TEST(32, gpr.R(MIPS_REG_FPCOND), Imm32(1));557558u32 notTakenTarget = ResolveNotTakenTarget(branchInfo);559CompBranchExits(cc, targetAddr, notTakenTarget, branchInfo);560}561562563void Jit::Comp_FPUBranch(MIPSOpcode op)564{565switch((op >> 16) & 0x1f)566{567case 0: BranchFPFlag(op, CC_NZ, false); break; //bc1f568case 1: BranchFPFlag(op, CC_Z, false); break; //bc1t569case 2: BranchFPFlag(op, CC_NZ, true); break; //bc1fl570case 3: BranchFPFlag(op, CC_Z, true); break; //bc1tl571default:572_dbg_assert_msg_(false,"Trying to interpret instruction that can't be interpreted");573break;574}575}576577// If likely is set, discard the branch slot if NOT taken.578void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)579{580CONDITIONAL_LOG;581if (js.inDelaySlot) {582// I think we can safely just warn-log this without reporting, it's pretty clear that this type583// of branch is ignored.584WARN_LOG(Log::JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);585return;586}587int offset = TARGET16;588u32 targetAddr = GetCompilerPC() + offset + 4;589590BranchInfo branchInfo(GetCompilerPC(), op, GetOffsetInstruction(1), false, likely);591// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)592// The behavior is undefined - the CPU may take the second branch even if the first one passes.593// However, it does consistently try each branch, which these games seem to expect.594branchInfo.delaySlotIsNice = IsDelaySlotNiceVFPU(op, branchInfo.delaySlotOp);595CONDITIONAL_NICE_DELAYSLOT;596597js.downcountAmount += MIPSGetInstructionCycleEstimate(branchInfo.delaySlotOp);598if (!likely && branchInfo.delaySlotIsNice && !branchInfo.delaySlotIsBranch)599CompileDelaySlot(DELAYSLOT_NICE);600601// THE CONDITION602int imm3 = (op >> 18) & 7;603604gpr.KillImmediate(MIPS_REG_VFPUCC, true, false);605TEST(32, gpr.R(MIPS_REG_VFPUCC), Imm32(1 << imm3));606607u32 notTakenTarget = ResolveNotTakenTarget(branchInfo);608CompBranchExits(cc, targetAddr, notTakenTarget, branchInfo);609}610611612void Jit::Comp_VBranch(MIPSOpcode op)613{614switch ((op >> 16) & 3)615{616case 0: BranchVFPUFlag(op, CC_NZ, false); break; //bvf617case 1: BranchVFPUFlag(op, CC_Z, false); break; //bvt618case 2: BranchVFPUFlag(op, CC_NZ, true); break; //bvfl619case 3: BranchVFPUFlag(op, CC_Z, true); break; //bvtl620default:621_dbg_assert_msg_(false,"Comp_VBranch: Invalid instruction");622break;623}624}625626static void HitInvalidJump(uint32_t dest) {627Core_ExecException(dest, currentMIPS->pc - 8, ExecExceptionType::JUMP);628}629630void Jit::Comp_Jump(MIPSOpcode op) {631CONDITIONAL_LOG;632if (js.inDelaySlot) {633ERROR_LOG_REPORT(Log::JIT, "Branch in Jump delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);634return;635}636u32 off = TARGET26;637u32 targetAddr = (GetCompilerPC() & 0xF0000000) | off;638639// Might be a stubbed address or something?640if (!Memory::IsValidAddress(targetAddr) || (targetAddr & 3) != 0) {641if (js.nextExit == 0) {642ERROR_LOG_REPORT(Log::JIT, "Jump to invalid address: %08x PC %08x LR %08x", targetAddr, GetCompilerPC(), currentMIPS->r[MIPS_REG_RA]);643} else {644js.compiling = false;645}646// TODO: Mark this block dirty or something? May be indication it will be changed by imports.647648CompileDelaySlot(DELAYSLOT_NICE);649FlushAll();650MOV(32, MIPSSTATE_VAR(pc), Imm32(GetCompilerPC() + 8));651ABI_CallFunctionC(&HitInvalidJump, targetAddr);652WriteSyscallExit();653return;654}655656switch (op >> 26) {657case 2: //j658CompileDelaySlot(DELAYSLOT_NICE);659if (CanContinueJump(targetAddr))660{661AddContinuedBlock(targetAddr);662// Account for the increment in the loop.663js.compilerPC = targetAddr - 4;664// In case the delay slot was a break or something.665js.compiling = true;666return;667}668FlushAll();669CONDITIONAL_LOG_EXIT(targetAddr);670WriteExit(targetAddr, js.nextExit++);671break;672673case 3: //jal674// Special case for branches to "replace functions":675if (ReplaceJalTo(targetAddr))676return;677678// Check for small function inlining (future)679680681// Save return address - might be overwritten by delay slot.682gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);683CompileDelaySlot(DELAYSLOT_NICE);684if (CanContinueJump(targetAddr))685{686AddContinuedBlock(targetAddr);687// Account for the increment in the loop.688js.compilerPC = targetAddr - 4;689// In case the delay slot was a break or something.690js.compiling = true;691return;692}693FlushAll();694CONDITIONAL_LOG_EXIT(targetAddr);695WriteExit(targetAddr, js.nextExit++);696break;697698default:699_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");700break;701}702js.compiling = false;703}704705void Jit::Comp_JumpReg(MIPSOpcode op)706{707CONDITIONAL_LOG;708if (js.inDelaySlot) {709ERROR_LOG_REPORT(Log::JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);710return;711}712MIPSGPReg rs = _RS;713MIPSGPReg rd = _RD;714bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;715716MIPSOpcode delaySlotOp = GetOffsetInstruction(1);717js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);718bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);719if (andLink && rs == rd)720delaySlotIsNice = false;721CONDITIONAL_NICE_DELAYSLOT;722723X64Reg destReg = EAX;724if (IsSyscall(delaySlotOp))725{726// If this is a syscall, write the pc (for thread switching and other good reasons.)727gpr.MapReg(rs, true, false);728MOV(32, MIPSSTATE_VAR(pc), gpr.R(rs));729if (andLink)730gpr.SetImm(rd, GetCompilerPC() + 8);731CompileDelaySlot(DELAYSLOT_FLUSH);732733// Syscalls write the exit code for us.734_dbg_assert_msg_(!js.compiling, "Expected syscall to write an exit code.");735return;736}737else if (delaySlotIsNice)738{739if (andLink)740gpr.SetImm(rd, GetCompilerPC() + 8);741CompileDelaySlot(DELAYSLOT_NICE);742743if (!andLink && rs == MIPS_REG_RA && g_Config.bDiscardRegsOnJRRA) {744// According to the MIPS ABI, there are some regs we don't need to preserve.745// Let's discard them so we don't need to write them back.746// NOTE: Not all games follow the MIPS ABI! Tekken 6, for example, will crash747// with this enabled.748gpr.DiscardRegContentsIfCached(MIPS_REG_COMPILER_SCRATCH);749for (int i = MIPS_REG_A0; i <= MIPS_REG_T7; i++)750gpr.DiscardRegContentsIfCached((MIPSGPReg)i);751gpr.DiscardRegContentsIfCached(MIPS_REG_T8);752gpr.DiscardRegContentsIfCached(MIPS_REG_T9);753}754755if (gpr.IsImm(rs) && CanContinueJump(gpr.GetImm(rs)))756{757AddContinuedBlock(gpr.GetImm(rs));758// Account for the increment in the loop.759js.compilerPC = gpr.GetImm(rs) - 4;760// In case the delay slot was a break or something.761js.compiling = true;762return;763}764765if (gpr.R(rs).IsSimpleReg()) {766destReg = gpr.R(rs).GetSimpleReg();767} else {768MOV(32, R(EAX), gpr.R(rs));769}770FlushAll();771} else {772// Latch destination now - save it in memory.773gpr.MapReg(rs, true, false);774MOV(32, MIPSSTATE_VAR(savedPC), gpr.R(rs));775if (andLink)776gpr.SetImm(rd, GetCompilerPC() + 8);777CompileDelaySlot(DELAYSLOT_NICE);778MOV(32, R(EAX), MIPSSTATE_VAR(savedPC));779FlushAll();780}781782switch (op & 0x3f) {783case 8: //jr784break;785case 9: //jalr786break;787default:788_dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");789break;790}791792CONDITIONAL_LOG_EXIT_EAX();793WriteExitDestInReg(destReg);794js.compiling = false;795}796797void Jit::Comp_Syscall(MIPSOpcode op)798{799if (op.encoding == 0x03FFFFcc) {800WARN_LOG(Log::JIT, "Encountered bad syscall instruction at %08x (%08x)", js.compilerPC, op.encoding);801}802803if (!g_Config.bSkipDeadbeefFilling)804{805// All of these will be overwritten with DEADBEEF anyway.806gpr.DiscardR(MIPS_REG_COMPILER_SCRATCH);807// We need to keep A0 - T3, which are used for args.808gpr.DiscardR(MIPS_REG_T4);809gpr.DiscardR(MIPS_REG_T5);810gpr.DiscardR(MIPS_REG_T6);811gpr.DiscardR(MIPS_REG_T7);812gpr.DiscardR(MIPS_REG_T8);813gpr.DiscardR(MIPS_REG_T9);814815gpr.DiscardR(MIPS_REG_HI);816gpr.DiscardR(MIPS_REG_LO);817}818FlushAll();819820// If we're in a delay slot, this is off by one.821const int offset = js.inDelaySlot ? -1 : 0;822WriteDowncount(offset);823RestoreRoundingMode();824js.downcountAmount = -offset;825826if (!js.inDelaySlot) {827MOV(32, MIPSSTATE_VAR(pc), Imm32(GetCompilerPC() + 4));828}829830#ifdef USE_PROFILER831// When profiling, we can't skip CallSyscall, since it times syscalls.832ABI_CallFunctionC(&CallSyscall, op.encoding);833#else834// Skip the CallSyscall where possible.835void *quickFunc = GetQuickSyscallFunc(op);836if (quickFunc)837ABI_CallFunctionP(quickFunc, (void *)GetSyscallFuncPointer(op));838else839ABI_CallFunctionC(&CallSyscall, op.encoding);840#endif841842ApplyRoundingMode();843WriteSyscallExit();844js.compiling = false;845}846847void Jit::Comp_Break(MIPSOpcode op)848{849Comp_Generic(op);850WriteSyscallExit();851js.compiling = false;852}853854} // namespace Mipscomp855856#endif // PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)857858859