CoCalc -- X64IRCompALU.cpp

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GitHub Repository: hrydgard/ppsspp
Path: blob/master/Core/MIPS/x86/X64IRCompALU.cpp
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// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include "Common/CPUDetect.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/x86/X64IRJit.h"
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#include "Core/MIPS/x86/X64IRRegCache.h"
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// This file contains compilation for integer / arithmetic / logic related instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.  No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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void X64JitBackend::CompIR_Arith(IRInst inst) {
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	CONDITIONAL_DISABLE;
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	bool allowPtrMath = inst.constant <= 0x7FFFFFFF;
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#ifdef MASKED_PSP_MEMORY
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	// Since we modify it, we can't safely.
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	allowPtrMath = false;
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#endif
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	switch (inst.op) {
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	case IROp::Add:
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		regs_.Map(inst);
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		if (inst.src1 == inst.src2) {
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			LEA(32, regs_.RX(inst.dest), MScaled(regs_.RX(inst.src1), 2, 0));
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		} else if (inst.dest == inst.src2) {
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			ADD(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		} else if (inst.dest == inst.src1) {
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			ADD(32, regs_.R(inst.dest), regs_.R(inst.src2));
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		} else {
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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			ADD(32, regs_.R(inst.dest), regs_.R(inst.src2));
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		}
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		break;
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	case IROp::Sub:
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		regs_.Map(inst);
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		if (inst.src1 == inst.src2) {
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			regs_.SetGPRImm(inst.dest, 0);
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		} else if (inst.dest == inst.src2) {
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			NEG(32, regs_.R(inst.src2));
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			ADD(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		} else if (inst.dest == inst.src1) {
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			SUB(32, regs_.R(inst.dest), regs_.R(inst.src2));
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		} else {
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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			SUB(32, regs_.R(inst.dest), regs_.R(inst.src2));
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		}
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		break;
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	case IROp::AddConst:
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		if (regs_.IsGPRMappedAsPointer(inst.dest) && inst.dest == inst.src1 && allowPtrMath) {
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			regs_.MarkGPRAsPointerDirty(inst.dest);
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			LEA(PTRBITS, regs_.RXPtr(inst.dest), MDisp(regs_.RXPtr(inst.dest), inst.constant));
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		} else {
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			regs_.Map(inst);
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			LEA(32, regs_.RX(inst.dest), MDisp(regs_.RX(inst.src1), inst.constant));
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		}
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		break;
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	case IROp::SubConst:
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		if (regs_.IsGPRMappedAsPointer(inst.dest) && inst.dest == inst.src1 && allowPtrMath) {
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			regs_.MarkGPRAsPointerDirty(inst.dest);
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			LEA(PTRBITS, regs_.RXPtr(inst.dest), MDisp(regs_.RXPtr(inst.dest), -(int)inst.constant));
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		} else {
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			regs_.Map(inst);
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			LEA(32, regs_.RX(inst.dest), MDisp(regs_.RX(inst.src1), -(int)inst.constant));
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		}
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		break;
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	case IROp::Neg:
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		regs_.Map(inst);
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		if (inst.dest != inst.src1) {
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		}
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		NEG(32, regs_.R(inst.dest));
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		break;
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	default:
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		INVALIDOP;
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		break;
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	}
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}
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void X64JitBackend::CompIR_Assign(IRInst inst) {
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	CONDITIONAL_DISABLE;
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	switch (inst.op) {
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	case IROp::Mov:
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		if (inst.dest != inst.src1) {
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			regs_.Map(inst);
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		}
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		break;
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	case IROp::Ext8to32:
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		regs_.MapWithFlags(inst, X64Map::NONE, X64Map::LOW_SUBREG);
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		MOVSX(32, 8, regs_.RX(inst.dest), regs_.R(inst.src1));
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		break;
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	case IROp::Ext16to32:
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		regs_.Map(inst);
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		MOVSX(32, 16, regs_.RX(inst.dest), regs_.R(inst.src1));
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		break;
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	default:
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		INVALIDOP;
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		break;
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	}
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}
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void X64JitBackend::CompIR_Bits(IRInst inst) {
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	CONDITIONAL_DISABLE;
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144
	switch (inst.op) {
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	case IROp::BSwap32:
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		regs_.Map(inst);
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		if (inst.src1 != inst.dest) {
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		}
150
		BSWAP(32, regs_.RX(inst.dest));
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		break;
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153
	case IROp::ReverseBits:
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		regs_.Map(inst);
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		if (inst.src1 != inst.dest) {
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		}
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		// Swap even/odd bits (in bits: 0123 -> 1032.)
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		LEA(32, SCRATCH1, MScaled(regs_.RX(inst.dest), 2, 0));
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		SHR(32, regs_.R(inst.dest), Imm8(1));
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		XOR(32, regs_.R(inst.dest), R(SCRATCH1));
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		AND(32, regs_.R(inst.dest), Imm32(0x55555555));
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		XOR(32, regs_.R(inst.dest), R(SCRATCH1));
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		// Swap pairs of bits (in bits: 10325476 -> 32107654.)
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		LEA(32, SCRATCH1, MScaled(regs_.RX(inst.dest), 4, 0));
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		SHR(32, regs_.R(inst.dest), Imm8(2));
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		XOR(32, regs_.R(inst.dest), R(SCRATCH1));
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		AND(32, regs_.R(inst.dest), Imm32(0x33333333));
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		XOR(32, regs_.R(inst.dest), R(SCRATCH1));
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173
		// Swap nibbles (in nibbles: ABCD -> BADC.)
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		MOV(32, R(SCRATCH1), regs_.R(inst.dest));
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		SHL(32, R(SCRATCH1), Imm8(4));
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		SHR(32, regs_.R(inst.dest), Imm8(4));
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		XOR(32, regs_.R(inst.dest), R(SCRATCH1));
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		AND(32, regs_.R(inst.dest), Imm32(0x0F0F0F0F));
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		XOR(32, regs_.R(inst.dest), R(SCRATCH1));
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		// Finally, swap the bytes to drop everything into place (nibbles: BADCFEHG -> HGFEDCBA.)
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		BSWAP(32, regs_.RX(inst.dest));
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		break;
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	case IROp::BSwap16:
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		regs_.Map(inst);
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		if (cpu_info.bBMI2) {
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			// Rotate to put it into the correct register, then swap.
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			if (inst.dest != inst.src1)
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				RORX(32, regs_.RX(inst.dest), regs_.R(inst.src1), 16);
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			else
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				ROR(32, regs_.R(inst.dest), Imm8(16));
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			BSWAP(32, regs_.RX(inst.dest));
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		} else {
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			if (inst.dest != inst.src1)
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				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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			BSWAP(32, regs_.RX(inst.dest));
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			ROR(32, regs_.R(inst.dest), Imm8(16));
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		}
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		break;
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	case IROp::Clz:
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		regs_.Map(inst);
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		if (cpu_info.bLZCNT) {
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			LZCNT(32, regs_.RX(inst.dest), regs_.R(inst.src1));
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		} else {
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			BSR(32, regs_.RX(inst.dest), regs_.R(inst.src1));
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			FixupBranch notFound = J_CC(CC_Z);
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			// Since one of these bits must be set, and none outside, this subtracts from 31.
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			XOR(32, regs_.R(inst.dest), Imm8(31));
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			FixupBranch skip = J();
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			SetJumpTarget(notFound);
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			MOV(32, regs_.R(inst.dest), Imm32(32));
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			SetJumpTarget(skip);
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		}
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		break;
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	default:
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		INVALIDOP;
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		break;
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	}
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}
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void X64JitBackend::CompIR_Compare(IRInst inst) {
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	CONDITIONAL_DISABLE;
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	auto setCC = [&](const OpArg &arg, CCFlags cc) {
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		// If it's carry, we can take advantage of ADC to avoid subregisters.
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		if (cc == CC_C && inst.dest != inst.src1 && inst.dest != inst.src2) {
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			XOR(32, regs_.R(inst.dest), regs_.R(inst.dest));
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			CMP(32, regs_.R(inst.src1), arg);
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			ADC(32, regs_.R(inst.dest), Imm8(0));
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		} else if (regs_.HasLowSubregister(regs_.RX(inst.dest)) && inst.dest != inst.src1 && inst.dest != inst.src2) {
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			XOR(32, regs_.R(inst.dest), regs_.R(inst.dest));
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			CMP(32, regs_.R(inst.src1), arg);
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			SETcc(cc, regs_.R(inst.dest));
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		} else {
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			CMP(32, regs_.R(inst.src1), arg);
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			SETcc(cc, R(SCRATCH1));
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			MOVZX(32, 8, regs_.RX(inst.dest), R(SCRATCH1));
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		}
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	};
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	switch (inst.op) {
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	case IROp::Slt:
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		regs_.Map(inst);
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		setCC(regs_.R(inst.src2), CC_L);
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		break;
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	case IROp::SltConst:
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		if (inst.constant == 0) {
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			// Basically, getting the sign bit.  Let's shift instead.
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			regs_.Map(inst);
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			if (inst.dest != inst.src1)
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				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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			SHR(32, regs_.R(inst.dest), Imm8(31));
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		} else {
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			regs_.Map(inst);
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			setCC(Imm32(inst.constant), CC_L);
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		}
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		break;
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	case IROp::SltU:
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		if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) {
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			// This is kinda common, same as != 0.  Avoid flushing src1.
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			regs_.SpillLockGPR(inst.src2, inst.dest);
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			regs_.MapGPR(inst.src2);
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			regs_.MapGPR(inst.dest, MIPSMap::NOINIT);
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			if (inst.dest != inst.src2 && regs_.HasLowSubregister(regs_.RX(inst.dest))) {
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				XOR(32, regs_.R(inst.dest), regs_.R(inst.dest));
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				TEST(32, regs_.R(inst.src2), regs_.R(inst.src2));
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				SETcc(CC_NE, regs_.R(inst.dest));
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			} else {
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				CMP(32, regs_.R(inst.src2), Imm8(0));
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				SETcc(CC_NE, R(SCRATCH1));
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				MOVZX(32, 8, regs_.RX(inst.dest), R(SCRATCH1));
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			}
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		} else {
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			regs_.Map(inst);
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			setCC(regs_.R(inst.src2), CC_B);
284
		}
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		break;
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	case IROp::SltUConst:
288
		if (inst.constant == 0) {
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			regs_.SetGPRImm(inst.dest, 0);
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		} else {
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			regs_.Map(inst);
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			setCC(Imm32(inst.constant), CC_B);
293
		}
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		break;
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	default:
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		INVALIDOP;
298
		break;
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	}
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}
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void X64JitBackend::CompIR_CondAssign(IRInst inst) {
303
	CONDITIONAL_DISABLE;
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305
	switch (inst.op) {
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	case IROp::MovZ:
307
		if (inst.dest != inst.src2) {
308
			regs_.Map(inst);
309
			TEST(32, regs_.R(inst.src1), regs_.R(inst.src1));
310
			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_Z);
311
		}
312
		break;
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314
	case IROp::MovNZ:
315
		if (inst.dest != inst.src2) {
316
			regs_.Map(inst);
317
			TEST(32, regs_.R(inst.src1), regs_.R(inst.src1));
318
			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_NZ);
319
		}
320
		break;
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	case IROp::Max:
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		regs_.Map(inst);
324
		if (inst.src1 == inst.src2) {
325
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
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		} else if (inst.dest == inst.src1) {
327
			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
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			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_L);
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		} else if (inst.dest == inst.src2) {
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			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
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			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src1), CC_G);
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		} else {
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			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
334
			CMP(32, regs_.R(inst.dest), regs_.R(inst.src2));
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			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_L);
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		}
337
		break;
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	case IROp::Min:
340
		regs_.Map(inst);
341
		if (inst.src1 == inst.src2) {
342
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
343
		} else if (inst.dest == inst.src1) {
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			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
345
			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_G);
346
		} else if (inst.dest == inst.src2) {
347
			CMP(32, regs_.R(inst.src1), regs_.R(inst.src2));
348
			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src1), CC_L);
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		} else {
350
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
351
			CMP(32, regs_.R(inst.dest), regs_.R(inst.src2));
352
			CMOVcc(32, regs_.RX(inst.dest), regs_.R(inst.src2), CC_G);
353
		}
354
		break;
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356
	default:
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		INVALIDOP;
358
		break;
359
	}
360
}
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362
void X64JitBackend::CompIR_Div(IRInst inst) {
363
	CONDITIONAL_DISABLE;
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365
	switch (inst.op) {
366
	case IROp::Div:
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#if PPSSPP_ARCH(AMD64)
368
		// We need EDX specifically, so force a spill (before spill locks happen.)
369
		regs_.MapGPR2(IRREG_LO, MIPSMap::NOINIT | X64Map::HIGH_DATA);
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		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT | X64Map::HIGH_DATA } });
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#else // PPSSPP_ARCH(X86)
372
		// Force a spill, it's HI in this path.
373
		regs_.MapGPR(IRREG_HI, MIPSMap::NOINIT | X64Map::HIGH_DATA);
374
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::NOINIT }, { 'G', IRREG_HI, 1, MIPSMap::NOINIT | X64Map::HIGH_DATA } });
375
#endif
376
		{
377
			TEST(32, regs_.R(inst.src2), regs_.R(inst.src2));
378
			FixupBranch divideByZero = J_CC(CC_E, false);
379

380
			// Sign extension sets HI to -1 for us on x64.
381
			MOV(PTRBITS, regs_.R(IRREG_LO), Imm32(0x80000000));
382
#if PPSSPP_ARCH(X86)
383
			MOV(PTRBITS, regs_.R(IRREG_HI), Imm32(-1));
384
#endif
385
			CMP(32, regs_.R(inst.src1), regs_.R(IRREG_LO));
386
			FixupBranch numeratorNotOverflow = J_CC(CC_NE, false);
387
			CMP(32, regs_.R(inst.src2), Imm32(-1));
388
			FixupBranch denominatorOverflow = J_CC(CC_E, false);
389

390
			SetJumpTarget(numeratorNotOverflow);
391

392
			// It's finally time to actually divide.
393
			MOV(32, R(EAX), regs_.R(inst.src1));
394
			CDQ();
395
			IDIV(32, regs_.R(inst.src2));
396
#if PPSSPP_ARCH(AMD64)
397
			// EDX == RX(IRREG_LO).  Put the remainder in the upper bits, done.
398
			SHL(64, R(EDX), Imm8(32));
399
			OR(64, R(EDX), R(EAX));
400
#else // PPSSPP_ARCH(X86)
401
			// EDX is already good (HI), just move EAX into place.
402
			MOV(32, regs_.R(IRREG_LO), R(EAX));
403
#endif
404
			FixupBranch done = J(false);
405

406
			SetJumpTarget(divideByZero);
407
			X64Reg loReg = SCRATCH1;
408
#if PPSSPP_ARCH(X86)
409
			if (regs_.HasLowSubregister(regs_.RX(IRREG_LO)))
410
				loReg = regs_.RX(IRREG_LO);
411
#endif
412
			// Set to -1 if numerator positive using SF.
413
			XOR(32, R(loReg), R(loReg));
414
			TEST(32, regs_.R(inst.src1), regs_.R(inst.src1));
415
			SETcc(CC_NS, R(loReg));
416
			NEG(32, R(loReg));
417
			// If it was negative, OR in 1 (so we get -1 or 1.)
418
			OR(32, R(loReg), Imm8(1));
419

420
#if PPSSPP_ARCH(AMD64)
421
			// Move the numerator into the high bits.
422
			MOV(32, regs_.R(IRREG_LO), regs_.R(inst.src1));
423
			SHL(64, regs_.R(IRREG_LO), Imm8(32));
424
			OR(64, regs_.R(IRREG_LO), R(loReg));
425
#else // PPSSPP_ARCH(X86)
426
			// If we didn't have a subreg, move into place.
427
			if (loReg != regs_.RX(IRREG_LO))
428
				MOV(32, regs_.R(IRREG_LO), R(loReg));
429
			MOV(32, regs_.R(IRREG_HI), regs_.R(inst.src1));
430
#endif
431

432
			SetJumpTarget(denominatorOverflow);
433
			SetJumpTarget(done);
434
		}
435
		break;
436

437
	case IROp::DivU:
438
#if PPSSPP_ARCH(AMD64)
439
		// We need EDX specifically, so force a spill (before spill locks happen.)
440
		regs_.MapGPR2(IRREG_LO, MIPSMap::NOINIT | X64Map::HIGH_DATA);
441
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT | X64Map::HIGH_DATA } });
442
#else // PPSSPP_ARCH(X86)
443
		// Force a spill, it's HI in this path.
444
		regs_.MapGPR(IRREG_HI, MIPSMap::NOINIT | X64Map::HIGH_DATA);
445
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::NOINIT }, { 'G', IRREG_HI, 1, MIPSMap::NOINIT | X64Map::HIGH_DATA } });
446
#endif
447
		{
448
			TEST(32, regs_.R(inst.src2), regs_.R(inst.src2));
449
			FixupBranch divideByZero = J_CC(CC_E, false);
450

451
			MOV(32, R(EAX), regs_.R(inst.src1));
452
			XOR(32, R(EDX), R(EDX));
453
			DIV(32, regs_.R(inst.src2));
454
#if PPSSPP_ARCH(AMD64)
455
			// EDX == RX(IRREG_LO).  Put the remainder in the upper bits, done.
456
			SHL(64, R(EDX), Imm8(32));
457
			OR(64, R(EDX), R(EAX));
458
#else // PPSSPP_ARCH(X86)
459
			// EDX is already good (HI), just move EAX into place.
460
			MOV(32, regs_.R(IRREG_LO), R(EAX));
461
#endif
462
			FixupBranch done = J(false);
463

464
			SetJumpTarget(divideByZero);
465
			// First, set LO to 0xFFFF if numerator was <= that value.
466
			MOV(32, regs_.R(IRREG_LO), Imm32(0xFFFF));
467
			XOR(32, R(SCRATCH1), R(SCRATCH1));
468
			CMP(32, regs_.R(IRREG_LO), regs_.R(inst.src1));
469
			// If 0xFFFF was less, CF was set - SBB will subtract 1 from 0, netting -1.
470
			SBB(32, R(SCRATCH1), Imm8(0));
471
			OR(32, regs_.R(IRREG_LO), R(SCRATCH1));
472

473
#if PPSSPP_ARCH(AMD64)
474
			// Move the numerator into the high bits.
475
			MOV(32, R(SCRATCH1), regs_.R(inst.src1));
476
			SHL(64, R(SCRATCH1), Imm8(32));
477
			OR(64, regs_.R(IRREG_LO), R(SCRATCH1));
478
#else // PPSSPP_ARCH(X86)
479
			MOV(32, regs_.R(IRREG_HI), regs_.R(inst.src1));
480
#endif
481

482
			SetJumpTarget(done);
483
		}
484
		break;
485

486
	default:
487
		INVALIDOP;
488
		break;
489
	}
490
}
491

492
void X64JitBackend::CompIR_HiLo(IRInst inst) {
493
	CONDITIONAL_DISABLE;
494

495
	switch (inst.op) {
496
	case IROp::MtLo:
497
#if PPSSPP_ARCH(AMD64)
498
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } });
499
		// First, clear the bits we're replacing.
500
		SHR(64, regs_.R(IRREG_LO), Imm8(32));
501
		SHL(64, regs_.R(IRREG_LO), Imm8(32));
502
		// Now clear the high bits and merge.
503
		MOVZX(64, 32, regs_.RX(inst.src1), regs_.R(inst.src1));
504
		OR(64, regs_.R(IRREG_LO), regs_.R(inst.src1));
505
#else // PPSSPP_ARCH(X86)
506
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::DIRTY } });
507
		MOV(32, regs_.R(IRREG_LO), regs_.R(inst.src1));
508
#endif
509
		break;
510

511
	case IROp::MtHi:
512
#if PPSSPP_ARCH(AMD64)
513
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } });
514
		// First, clear the bits we're replacing.
515
		MOVZX(64, 32, regs_.RX(IRREG_LO), regs_.R(IRREG_LO));
516
		// Then move the new bits into place.
517
		MOV(32, R(SCRATCH1), regs_.R(inst.src1));
518
		SHL(64, R(SCRATCH1), Imm8(32));
519
		OR(64, regs_.R(IRREG_LO), R(SCRATCH1));
520
#else // PPSSPP_ARCH(X86)
521
		regs_.MapWithExtra(inst, { { 'G', IRREG_HI, 1, MIPSMap::DIRTY } });
522
		MOV(32, regs_.R(IRREG_HI), regs_.R(inst.src1));
523
#endif
524
		break;
525

526
	case IROp::MfLo:
527
#if PPSSPP_ARCH(AMD64)
528
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::INIT } });
529
		MOV(32, regs_.R(inst.dest), regs_.R(IRREG_LO));
530
#else // PPSSPP_ARCH(X86)
531
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::INIT } });
532
		MOV(32, regs_.R(inst.dest), regs_.R(IRREG_LO));
533
#endif
534
		break;
535

536
	case IROp::MfHi:
537
#if PPSSPP_ARCH(AMD64)
538
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::INIT } });
539
		MOV(64, regs_.R(inst.dest), regs_.R(IRREG_LO));
540
		SHR(64, regs_.R(inst.dest), Imm8(32));
541
#else // PPSSPP_ARCH(X86)
542
		regs_.MapWithExtra(inst, { { 'G', IRREG_HI, 1, MIPSMap::INIT } });
543
		MOV(32, regs_.R(inst.dest), regs_.R(IRREG_HI));
544
#endif
545
		break;
546

547
	default:
548
		INVALIDOP;
549
		break;
550
	}
551
}
552

553
void X64JitBackend::CompIR_Logic(IRInst inst) {
554
	CONDITIONAL_DISABLE;
555

556
	switch (inst.op) {
557
	case IROp::And:
558
		regs_.Map(inst);
559
		if (inst.dest == inst.src1) {
560
			AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
561
		} else if (inst.dest == inst.src2) {
562
			AND(32, regs_.R(inst.dest), regs_.R(inst.src1));
563
		} else {
564
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
565
			AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
566
		}
567
		break;
568

569
	case IROp::Or:
570
		regs_.Map(inst);
571
		if (inst.dest == inst.src1) {
572
			OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
573
		} else if (inst.dest == inst.src2) {
574
			OR(32, regs_.R(inst.dest), regs_.R(inst.src1));
575
		} else {
576
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
577
			OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
578
		}
579
		break;
580

581
	case IROp::Xor:
582
		regs_.Map(inst);
583
		if (inst.dest == inst.src1) {
584
			XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
585
		} else if (inst.dest == inst.src2) {
586
			XOR(32, regs_.R(inst.dest), regs_.R(inst.src1));
587
		} else {
588
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
589
			XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
590
		}
591
		break;
592

593
	case IROp::AndConst:
594
		regs_.Map(inst);
595
		if (inst.dest != inst.src1)
596
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
597
		AND(32, regs_.R(inst.dest), SImmAuto((s32)inst.constant));
598
		break;
599

600
	case IROp::OrConst:
601
		regs_.Map(inst);
602
		if (inst.dest != inst.src1)
603
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
604
		OR(32, regs_.R(inst.dest), SImmAuto((s32)inst.constant));
605
		break;
606

607
	case IROp::XorConst:
608
		regs_.Map(inst);
609
		if (inst.dest != inst.src1)
610
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
611
		XOR(32, regs_.R(inst.dest), SImmAuto((s32)inst.constant));
612
		break;
613

614
	case IROp::Not:
615
		regs_.Map(inst);
616
		if (inst.dest != inst.src1)
617
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
618
		NOT(32, regs_.R(inst.dest));
619
		break;
620

621
	default:
622
		INVALIDOP;
623
		break;
624
	}
625
}
626

627
void X64JitBackend::CompIR_Mult(IRInst inst) {
628
	CONDITIONAL_DISABLE;
629

630
	switch (inst.op) {
631
	case IROp::Mult:
632
#if PPSSPP_ARCH(AMD64)
633
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT } });
634
		MOVSX(64, 32, regs_.RX(IRREG_LO), regs_.R(inst.src1));
635
		MOVSX(64, 32, regs_.RX(inst.src2), regs_.R(inst.src2));
636
		IMUL(64, regs_.RX(IRREG_LO), regs_.R(inst.src2));
637
#else // PPSSPP_ARCH(X86)
638
		// Force a spill (before spill locks.)
639
		regs_.MapGPR(IRREG_HI, MIPSMap::NOINIT | X64Map::HIGH_DATA);
640
		// We keep it here so it stays locked.
641
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::NOINIT }, { 'G', IRREG_HI, 1, MIPSMap::NOINIT | X64Map::HIGH_DATA } });
642
		MOV(32, R(EAX), regs_.R(inst.src1));
643
		IMUL(32, regs_.R(inst.src2));
644
		MOV(32, regs_.R(IRREG_LO), R(EAX));
645
		// IRREG_HI was mapped to EDX.
646
#endif
647
		break;
648

649
	case IROp::MultU:
650
#if PPSSPP_ARCH(AMD64)
651
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT } });
652
		MOVZX(64, 32, regs_.RX(IRREG_LO), regs_.R(inst.src1));
653
		MOVZX(64, 32, regs_.RX(inst.src2), regs_.R(inst.src2));
654
		IMUL(64, regs_.RX(IRREG_LO), regs_.R(inst.src2));
655
#else // PPSSPP_ARCH(X86)
656
		// Force a spill (before spill locks.)
657
		regs_.MapGPR(IRREG_HI, MIPSMap::NOINIT | X64Map::HIGH_DATA);
658
		// We keep it here so it stays locked.
659
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::NOINIT }, { 'G', IRREG_HI, 1, MIPSMap::NOINIT | X64Map::HIGH_DATA } });
660
		MOV(32, R(EAX), regs_.R(inst.src1));
661
		MUL(32, regs_.R(inst.src2));
662
		MOV(32, regs_.R(IRREG_LO), R(EAX));
663
		// IRREG_HI was mapped to EDX.
664
#endif
665
		break;
666

667
	case IROp::Madd:
668
#if PPSSPP_ARCH(AMD64)
669
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } });
670
		MOVSX(64, 32, SCRATCH1, regs_.R(inst.src1));
671
		MOVSX(64, 32, regs_.RX(inst.src2), regs_.R(inst.src2));
672
		IMUL(64, SCRATCH1, regs_.R(inst.src2));
673
		ADD(64, regs_.R(IRREG_LO), R(SCRATCH1));
674
#else // PPSSPP_ARCH(X86)
675
		// For ones that modify LO/HI, we can't have anything else in EDX.
676
		regs_.ReserveAndLockXGPR(EDX);
677
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::DIRTY }, { 'G', IRREG_HI, 1, MIPSMap::DIRTY } });
678
		MOV(32, R(EAX), regs_.R(inst.src1));
679
		IMUL(32, regs_.R(inst.src2));
680
		ADD(32, regs_.R(IRREG_LO), R(EAX));
681
		ADC(32, regs_.R(IRREG_HI), R(EDX));
682
#endif
683
		break;
684

685
	case IROp::MaddU:
686
#if PPSSPP_ARCH(AMD64)
687
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } });
688
		MOVZX(64, 32, SCRATCH1, regs_.R(inst.src1));
689
		MOVZX(64, 32, regs_.RX(inst.src2), regs_.R(inst.src2));
690
		IMUL(64, SCRATCH1, regs_.R(inst.src2));
691
		ADD(64, regs_.R(IRREG_LO), R(SCRATCH1));
692
#else // PPSSPP_ARCH(X86)
693
		// For ones that modify LO/HI, we can't have anything else in EDX.
694
		regs_.ReserveAndLockXGPR(EDX);
695
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::DIRTY }, { 'G', IRREG_HI, 1, MIPSMap::DIRTY } });
696
		MOV(32, R(EAX), regs_.R(inst.src1));
697
		MUL(32, regs_.R(inst.src2));
698
		ADD(32, regs_.R(IRREG_LO), R(EAX));
699
		ADC(32, regs_.R(IRREG_HI), R(EDX));
700
#endif
701
		break;
702

703
	case IROp::Msub:
704
#if PPSSPP_ARCH(AMD64)
705
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } });
706
		MOVSX(64, 32, SCRATCH1, regs_.R(inst.src1));
707
		MOVSX(64, 32, regs_.RX(inst.src2), regs_.R(inst.src2));
708
		IMUL(64, SCRATCH1, regs_.R(inst.src2));
709
		SUB(64, regs_.R(IRREG_LO), R(SCRATCH1));
710
#else // PPSSPP_ARCH(X86)
711
		// For ones that modify LO/HI, we can't have anything else in EDX.
712
		regs_.ReserveAndLockXGPR(EDX);
713
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::DIRTY }, { 'G', IRREG_HI, 1, MIPSMap::DIRTY } });
714
		MOV(32, R(EAX), regs_.R(inst.src1));
715
		IMUL(32, regs_.R(inst.src2));
716
		SUB(32, regs_.R(IRREG_LO), R(EAX));
717
		SBB(32, regs_.R(IRREG_HI), R(EDX));
718
#endif
719
		break;
720

721
	case IROp::MsubU:
722
#if PPSSPP_ARCH(AMD64)
723
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } });
724
		MOVZX(64, 32, SCRATCH1, regs_.R(inst.src1));
725
		MOVZX(64, 32, regs_.RX(inst.src2), regs_.R(inst.src2));
726
		IMUL(64, SCRATCH1, regs_.R(inst.src2));
727
		SUB(64, regs_.R(IRREG_LO), R(SCRATCH1));
728
#else // PPSSPP_ARCH(X86)
729
		// For ones that modify LO/HI, we can't have anything else in EDX.
730
		regs_.ReserveAndLockXGPR(EDX);
731
		regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 1, MIPSMap::DIRTY }, { 'G', IRREG_HI, 1, MIPSMap::DIRTY } });
732
		MOV(32, R(EAX), regs_.R(inst.src1));
733
		MUL(32, regs_.R(inst.src2));
734
		SUB(32, regs_.R(IRREG_LO), R(EAX));
735
		SBB(32, regs_.R(IRREG_HI), R(EDX));
736
#endif
737
		break;
738

739
	default:
740
		INVALIDOP;
741
		break;
742
	}
743
}
744

745
void X64JitBackend::CompIR_Shift(IRInst inst) {
746
	CONDITIONAL_DISABLE;
747

748
	switch (inst.op) {
749
	case IROp::Shl:
750
		if (cpu_info.bBMI2) {
751
			regs_.Map(inst);
752
			SHLX(32, regs_.RX(inst.dest), regs_.R(inst.src1), regs_.RX(inst.src2));
753
		} else {
754
			regs_.MapWithFlags(inst, X64Map::NONE, X64Map::NONE, X64Map::SHIFT);
755
			if (inst.dest == inst.src1) {
756
				SHL(32, regs_.R(inst.dest), regs_.R(inst.src2));
757
			} else if (inst.dest == inst.src2) {
758
				MOV(32, R(SCRATCH1), regs_.R(inst.src1));
759
				SHL(32, R(SCRATCH1), regs_.R(inst.src2));
760
				MOV(32, regs_.R(inst.dest), R(SCRATCH1));
761
			} else {
762
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
763
				SHL(32, regs_.R(inst.dest), regs_.R(inst.src2));
764
			}
765
		}
766
		break;
767

768
	case IROp::Shr:
769
		if (cpu_info.bBMI2) {
770
			regs_.Map(inst);
771
			SHRX(32, regs_.RX(inst.dest), regs_.R(inst.src1), regs_.RX(inst.src2));
772
		} else {
773
			regs_.MapWithFlags(inst, X64Map::NONE, X64Map::NONE, X64Map::SHIFT);
774
			if (inst.dest == inst.src1) {
775
				SHR(32, regs_.R(inst.dest), regs_.R(inst.src2));
776
			} else if (inst.dest == inst.src2) {
777
				MOV(32, R(SCRATCH1), regs_.R(inst.src1));
778
				SHR(32, R(SCRATCH1), regs_.R(inst.src2));
779
				MOV(32, regs_.R(inst.dest), R(SCRATCH1));
780
			} else {
781
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
782
				SHR(32, regs_.R(inst.dest), regs_.R(inst.src2));
783
			}
784
		}
785
		break;
786

787
	case IROp::Sar:
788
		if (cpu_info.bBMI2) {
789
			regs_.Map(inst);
790
			SARX(32, regs_.RX(inst.dest), regs_.R(inst.src1), regs_.RX(inst.src2));
791
		} else {
792
			regs_.MapWithFlags(inst, X64Map::NONE, X64Map::NONE, X64Map::SHIFT);
793
			if (inst.dest == inst.src1) {
794
				SAR(32, regs_.R(inst.dest), regs_.R(inst.src2));
795
			} else if (inst.dest == inst.src2) {
796
				MOV(32, R(SCRATCH1), regs_.R(inst.src1));
797
				SAR(32, R(SCRATCH1), regs_.R(inst.src2));
798
				MOV(32, regs_.R(inst.dest), R(SCRATCH1));
799
			} else {
800
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
801
				SAR(32, regs_.R(inst.dest), regs_.R(inst.src2));
802
			}
803
		}
804
		break;
805

806
	case IROp::Ror:
807
		regs_.MapWithFlags(inst, X64Map::NONE, X64Map::NONE, X64Map::SHIFT);
808
		if (inst.dest == inst.src1) {
809
			ROR(32, regs_.R(inst.dest), regs_.R(inst.src2));
810
		} else if (inst.dest == inst.src2) {
811
			MOV(32, R(SCRATCH1), regs_.R(inst.src1));
812
			ROR(32, R(SCRATCH1), regs_.R(inst.src2));
813
			MOV(32, regs_.R(inst.dest), R(SCRATCH1));
814
		} else {
815
			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
816
			ROR(32, regs_.R(inst.dest), regs_.R(inst.src2));
817
		}
818
		break;
819

820
	case IROp::ShlImm:
821
		// Shouldn't happen, but let's be safe of any passes that modify the ops.
822
		if (inst.src2 >= 32) {
823
			regs_.SetGPRImm(inst.dest, 0);
824
		} else if (inst.src2 == 0) {
825
			if (inst.dest != inst.src1) {
826
				regs_.Map(inst);
827
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
828
			}
829
		} else if (inst.src2 <= 3) {
830
			regs_.Map(inst);
831
			LEA(32, regs_.RX(inst.dest), MScaled(regs_.RX(inst.src1), 1 << inst.src2, 0));
832
		} else {
833
			regs_.Map(inst);
834
			if (inst.dest != inst.src1)
835
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
836
			SHL(32, regs_.R(inst.dest), Imm8(inst.src2));
837
		}
838
		break;
839

840
	case IROp::ShrImm:
841
		// Shouldn't happen, but let's be safe of any passes that modify the ops.
842
		if (inst.src2 >= 32) {
843
			regs_.SetGPRImm(inst.dest, 0);
844
		} else if (inst.src2 == 0) {
845
			if (inst.dest != inst.src1) {
846
				regs_.Map(inst);
847
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
848
			}
849
		} else {
850
			regs_.Map(inst);
851
			if (inst.dest != inst.src1)
852
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
853
			SHR(32, regs_.R(inst.dest), Imm8(inst.src2));
854
		}
855
		break;
856

857
	case IROp::SarImm:
858
		// Shouldn't happen, but let's be safe of any passes that modify the ops.
859
		if (inst.src2 >= 32) {
860
			regs_.Map(inst);
861
			if (inst.dest != inst.src1)
862
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
863
			SAR(32, regs_.R(inst.dest), Imm8(31));
864
		} else if (inst.src2 == 0) {
865
			if (inst.dest != inst.src1) {
866
				regs_.Map(inst);
867
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
868
			}
869
		} else {
870
			regs_.Map(inst);
871
			if (inst.dest != inst.src1)
872
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
873
			SAR(32, regs_.R(inst.dest), Imm8(inst.src2));
874
		}
875
		break;
876

877
	case IROp::RorImm:
878
		if (inst.src2 == 0) {
879
			if (inst.dest != inst.src1) {
880
				regs_.Map(inst);
881
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
882
			}
883
		} else if (cpu_info.bBMI2) {
884
			regs_.Map(inst);
885
			RORX(32, regs_.RX(inst.dest), regs_.R(inst.src1), inst.src2 & 31);
886
		} else {
887
			regs_.Map(inst);
888
			if (inst.dest != inst.src1)
889
				MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
890
			ROR(32, regs_.R(inst.dest), Imm8(inst.src2 & 31));
891
		}
892
		break;
893

894
	default:
895
		INVALIDOP;
896
		break;
897
	}
898
}
899

900
} // namespace MIPSComp
901

902
#endif
903

904
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