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Path: blob/master/Core/MIPS/x86/X64IRCompLoadStore.cpp
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "ppsspp_config.h"18#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)1920#include "Core/MemMap.h"21#include "Core/MIPS/x86/X64IRJit.h"22#include "Core/MIPS/x86/X64IRRegCache.h"2324// This file contains compilation for load/store instructions.25//26// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.27// Currently known non working ones should have DISABLE. No flags because that's in IR already.2829// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }30#define CONDITIONAL_DISABLE {}31#define DISABLE { CompIR_Generic(inst); return; }32#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }3334namespace MIPSComp {3536using namespace Gen;37using namespace X64IRJitConstants;3839Gen::OpArg X64JitBackend::PrepareSrc1Address(IRInst inst) {40const IRMeta *m = GetIRMeta(inst.op);4142bool src1IsPointer = regs_.IsGPRMappedAsPointer(inst.src1);43bool readsFromSrc1 = inst.src1 == inst.src3 && (m->flags & (IRFLAG_SRC3 | IRFLAG_SRC3DST)) != 0;44// If it's about to be clobbered, don't waste time pointerifying. Use displacement.45bool clobbersSrc1 = !readsFromSrc1 && regs_.IsGPRClobbered(inst.src1);4647int32_t disp = (int32_t)inst.constant;48// It can't be this negative, must be a constant address with the top bit set.49if ((disp & 0xC0000000) == 0x80000000) {50disp = inst.constant & 0x7FFFFFFF;51}5253#ifdef MASKED_PSP_MEMORY54if (disp > 0)55disp &= Memory::MEMVIEW32_MASK;56#endif5758OpArg addrArg;59if (inst.src1 == MIPS_REG_ZERO) {60#ifdef MASKED_PSP_MEMORY61disp &= Memory::MEMVIEW32_MASK;62#endif63#if PPSSPP_ARCH(AMD64)64addrArg = MDisp(MEMBASEREG, disp & 0x7FFFFFFF);65#else66addrArg = M(Memory::base + disp);67#endif68} else if ((jo.cachePointers || src1IsPointer) && !readsFromSrc1 && (!clobbersSrc1 || src1IsPointer)) {69X64Reg src1 = regs_.MapGPRAsPointer(inst.src1);70addrArg = MDisp(src1, disp);71} else {72regs_.MapGPR(inst.src1);73#ifdef MASKED_PSP_MEMORY74LEA(PTRBITS, SCRATCH1, MDisp(regs_.RX(inst.src1), disp));75AND(PTRBITS, R(SCRATCH1), Imm32(Memory::MEMVIEW32_MASK));76addrArg = MDisp(SCRATCH1, (intptr_t)Memory::base);77#else78#if PPSSPP_ARCH(AMD64)79addrArg = MComplex(MEMBASEREG, regs_.RX(inst.src1), SCALE_1, disp);80#else81addrArg = MDisp(regs_.RX(inst.src1), Memory::base + disp);82#endif83#endif84}8586return addrArg;87}8889void X64JitBackend::CompIR_CondStore(IRInst inst) {90CONDITIONAL_DISABLE;91if (inst.op != IROp::Store32Conditional)92INVALIDOP;9394regs_.SpillLockGPR(IRREG_LLBIT, inst.src3, inst.src1);95OpArg addrArg = PrepareSrc1Address(inst);96OpArg valueArg = R(regs_.MapGPR(inst.src3, MIPSMap::INIT));9798regs_.MapGPR(IRREG_LLBIT, MIPSMap::INIT);99100// TODO: Safe memory? Or enough to have crash handler + validate?101102TEST(32, regs_.R(IRREG_LLBIT), regs_.R(IRREG_LLBIT));103FixupBranch condFailed = J_CC(CC_Z);104MOV(32, addrArg, valueArg);105106if (inst.dest != MIPS_REG_ZERO) {107MOV(32, regs_.R(inst.dest), Imm32(1));108FixupBranch finish = J();109110SetJumpTarget(condFailed);111XOR(32, regs_.R(inst.dest), regs_.R(inst.dest));112SetJumpTarget(finish);113} else {114SetJumpTarget(condFailed);115}116}117118void X64JitBackend::CompIR_FLoad(IRInst inst) {119CONDITIONAL_DISABLE;120121OpArg addrArg = PrepareSrc1Address(inst);122123switch (inst.op) {124case IROp::LoadFloat:125regs_.MapFPR(inst.dest, MIPSMap::NOINIT);126MOVSS(regs_.FX(inst.dest), addrArg);127break;128129default:130INVALIDOP;131break;132}133}134135void X64JitBackend::CompIR_FStore(IRInst inst) {136CONDITIONAL_DISABLE;137138OpArg addrArg = PrepareSrc1Address(inst);139140switch (inst.op) {141case IROp::StoreFloat:142regs_.MapFPR(inst.src3);143MOVSS(addrArg, regs_.FX(inst.src3));144break;145146default:147INVALIDOP;148break;149}150}151152void X64JitBackend::CompIR_Load(IRInst inst) {153CONDITIONAL_DISABLE;154155regs_.SpillLockGPR(inst.dest, inst.src1);156OpArg addrArg = PrepareSrc1Address(inst);157// With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1.158regs_.MapGPR(inst.dest, MIPSMap::NOINIT);159160// TODO: Safe memory? Or enough to have crash handler + validate?161162switch (inst.op) {163case IROp::Load8:164MOVZX(32, 8, regs_.RX(inst.dest), addrArg);165break;166167case IROp::Load8Ext:168MOVSX(32, 8, regs_.RX(inst.dest), addrArg);169break;170171case IROp::Load16:172MOVZX(32, 16, regs_.RX(inst.dest), addrArg);173break;174175case IROp::Load16Ext:176MOVSX(32, 16, regs_.RX(inst.dest), addrArg);177break;178179case IROp::Load32:180MOV(32, regs_.R(inst.dest), addrArg);181break;182183case IROp::Load32Linked:184if (inst.dest != MIPS_REG_ZERO)185MOV(32, regs_.R(inst.dest), addrArg);186regs_.SetGPRImm(IRREG_LLBIT, 1);187break;188189default:190INVALIDOP;191break;192}193}194195void X64JitBackend::CompIR_LoadShift(IRInst inst) {196CONDITIONAL_DISABLE;197198switch (inst.op) {199case IROp::Load32Left:200case IROp::Load32Right:201// Should not happen if the pass to split is active.202DISABLE;203break;204205default:206INVALIDOP;207break;208}209}210211void X64JitBackend::CompIR_Store(IRInst inst) {212CONDITIONAL_DISABLE;213214regs_.SpillLockGPR(inst.src3, inst.src1);215OpArg addrArg = PrepareSrc1Address(inst);216217// i386 can only use certain regs for 8-bit operations.218X64Map valueFlags = inst.op == IROp::Store8 ? X64Map::LOW_SUBREG : X64Map::NONE;219220OpArg valueArg;221X64Reg valueReg = regs_.TryMapTempImm(inst.src3, valueFlags);222if (valueReg != INVALID_REG) {223valueArg = R(valueReg);224} else if (regs_.IsGPRImm(inst.src3)) {225u32 imm = regs_.GetGPRImm(inst.src3);226switch (inst.op) {227case IROp::Store8: valueArg = Imm8((u8)imm); break;228case IROp::Store16: valueArg = Imm16((u16)imm); break;229case IROp::Store32: valueArg = Imm32(imm); break;230default:231INVALIDOP;232break;233}234} else {235valueArg = R(regs_.MapGPR(inst.src3, MIPSMap::INIT | valueFlags));236}237238// TODO: Safe memory? Or enough to have crash handler + validate?239240switch (inst.op) {241case IROp::Store8:242MOV(8, addrArg, valueArg);243break;244245case IROp::Store16:246MOV(16, addrArg, valueArg);247break;248249case IROp::Store32:250MOV(32, addrArg, valueArg);251break;252253default:254INVALIDOP;255break;256}257}258259void X64JitBackend::CompIR_StoreShift(IRInst inst) {260CONDITIONAL_DISABLE;261262switch (inst.op) {263case IROp::Store32Left:264case IROp::Store32Right:265// Should not happen if the pass to split is active.266DISABLE;267break;268269default:270INVALIDOP;271break;272}273}274275void X64JitBackend::CompIR_VecLoad(IRInst inst) {276CONDITIONAL_DISABLE;277278OpArg addrArg = PrepareSrc1Address(inst);279280switch (inst.op) {281case IROp::LoadVec4:282regs_.MapVec4(inst.dest, MIPSMap::NOINIT);283MOVUPS(regs_.FX(inst.dest), addrArg);284break;285286default:287INVALIDOP;288break;289}290}291292void X64JitBackend::CompIR_VecStore(IRInst inst) {293CONDITIONAL_DISABLE;294295OpArg addrArg = PrepareSrc1Address(inst);296297switch (inst.op) {298case IROp::StoreVec4:299regs_.MapVec4(inst.src3);300MOVUPS(addrArg, regs_.FX(inst.src3));301break;302303default:304INVALIDOP;305break;306}307}308309} // namespace MIPSComp310311#endif312313314