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Path: blob/master/Core/MIPS/x86/X64IRCompSystem.cpp
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// Copyright (c) 2023- PPSSPP Project.12// This program is free software: you can redistribute it and/or modify3// it under the terms of the GNU General Public License as published by4// the Free Software Foundation, version 2.0 or later versions.56// This program is distributed in the hope that it will be useful,7// but WITHOUT ANY WARRANTY; without even the implied warranty of8// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the9// GNU General Public License 2.0 for more details.1011// A copy of the GPL 2.0 should have been included with the program.12// If not, see http://www.gnu.org/licenses/1314// Official git repository and contact information can be found at15// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.1617#include "ppsspp_config.h"18#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)1920#include "Common/Profiler/Profiler.h"21#include "Core/Core.h"22#include "Core/Debugger/Breakpoints.h"23#include "Core/HLE/HLE.h"24#include "Core/HLE/ReplaceTables.h"25#include "Core/MemMap.h"26#include "Core/MIPS/MIPSAnalyst.h"27#include "Core/MIPS/IR/IRInterpreter.h"28#include "Core/MIPS/x86/X64IRJit.h"29#include "Core/MIPS/x86/X64IRRegCache.h"3031// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc.32//33// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.34// Currently known non working ones should have DISABLE. No flags because that's in IR already.3536// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }37#define CONDITIONAL_DISABLE {}38#define DISABLE { CompIR_Generic(inst); return; }39#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }4041namespace MIPSComp {4243using namespace Gen;44using namespace X64IRJitConstants;4546void X64JitBackend::CompIR_Basic(IRInst inst) {47CONDITIONAL_DISABLE;4849switch (inst.op) {50case IROp::Downcount:51// As long as we don't care about flags, just use LEA.52if (jo.downcountInRegister)53LEA(32, DOWNCOUNTREG, MDisp(DOWNCOUNTREG, -(s32)inst.constant));54else55SUB(32, MDisp(CTXREG, downcountOffset), SImmAuto((s32)inst.constant));56break;5758case IROp::SetConst:59regs_.SetGPRImm(inst.dest, inst.constant);60break;6162case IROp::SetConstF:63regs_.Map(inst);64if (inst.constant == 0) {65XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));66} else if (inst.constant == 0x7FFFFFFF) {67MOVSS(regs_.FX(inst.dest), M(constants.noSignMask)); // rip accessible68} else if (inst.constant == 0x80000000) {69MOVSS(regs_.FX(inst.dest), M(constants.signBitAll)); // rip accessible70} else if (inst.constant == 0x7F800000) {71MOVSS(regs_.FX(inst.dest), M(constants.positiveInfinity)); // rip accessible72} else if (inst.constant == 0x7FC00000) {73MOVSS(regs_.FX(inst.dest), M(constants.qNAN)); // rip accessible74} else if (inst.constant == 0x3F800000) {75MOVSS(regs_.FX(inst.dest), M(constants.positiveOnes)); // rip accessible76} else if (inst.constant == 0xBF800000) {77MOVSS(regs_.FX(inst.dest), M(constants.negativeOnes)); // rip accessible78} else if (inst.constant == 0x4EFFFFFF) {79MOVSS(regs_.FX(inst.dest), M(constants.maxIntBelowAsFloat)); // rip accessible80} else {81MOV(32, R(SCRATCH1), Imm32(inst.constant));82MOVD_xmm(regs_.FX(inst.dest), R(SCRATCH1));83}84break;8586case IROp::SetPC:87regs_.Map(inst);88MovToPC(regs_.RX(inst.src1));89break;9091case IROp::SetPCConst:92lastConstPC_ = inst.constant;93MOV(32, R(SCRATCH1), Imm32(inst.constant));94MovToPC(SCRATCH1);95break;9697default:98INVALIDOP;99break;100}101}102103void X64JitBackend::CompIR_Breakpoint(IRInst inst) {104CONDITIONAL_DISABLE;105106switch (inst.op) {107case IROp::Breakpoint:108FlushAll();109// Note: the constant could be a delay slot.110ABI_CallFunctionC((const void *)&IRRunBreakpoint, inst.constant);111TEST(32, R(EAX), R(EAX));112J_CC(CC_NZ, dispatcherCheckCoreState_, true);113break;114115case IROp::MemoryCheck:116if (regs_.IsGPRImm(inst.src1)) {117uint32_t iaddr = regs_.GetGPRImm(inst.src1) + inst.constant;118uint32_t checkedPC = lastConstPC_ + inst.dest;119int size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);120if (size == 0) {121checkedPC += 4;122size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);123}124bool isWrite = MIPSAnalyst::IsOpMemoryWrite(checkedPC);125126MemCheck check;127if (CBreakPoints::GetMemCheckInRange(iaddr, size, &check)) {128if (!(check.cond & MEMCHECK_READ) && !isWrite)129break;130if (!(check.cond & (MEMCHECK_WRITE | MEMCHECK_WRITE_ONCHANGE)) && isWrite)131break;132133// We need to flush, or conditions and log expressions will see old register values.134FlushAll();135136ABI_CallFunctionCC((const void *)&IRRunMemCheck, checkedPC, iaddr);137TEST(32, R(EAX), R(EAX));138J_CC(CC_NZ, dispatcherCheckCoreState_, true);139}140} else {141uint32_t checkedPC = lastConstPC_ + inst.dest;142int size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);143if (size == 0) {144checkedPC += 4;145size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);146}147bool isWrite = MIPSAnalyst::IsOpMemoryWrite(checkedPC);148149const auto memchecks = CBreakPoints::GetMemCheckRanges(isWrite);150// We can trivially skip if there are no checks for this type (i.e. read vs write.)151if (memchecks.empty())152break;153154X64Reg addrBase = regs_.MapGPR(inst.src1);155LEA(32, SCRATCH1, MDisp(addrBase, inst.constant));156157// We need to flush, or conditions and log expressions will see old register values.158FlushAll();159160std::vector<FixupBranch> hitChecks;161for (const auto &it : memchecks) {162if (it.end != 0) {163CMP(32, R(SCRATCH1), Imm32(it.start - size));164FixupBranch skipNext = J_CC(CC_BE);165166CMP(32, R(SCRATCH1), Imm32(it.end));167hitChecks.push_back(J_CC(CC_B, true));168169SetJumpTarget(skipNext);170} else {171CMP(32, R(SCRATCH1), Imm32(it.start));172hitChecks.push_back(J_CC(CC_E, true));173}174}175176FixupBranch noHits = J(true);177178// Okay, now land any hit here.179for (auto &fixup : hitChecks)180SetJumpTarget(fixup);181hitChecks.clear();182183ABI_CallFunctionAA((const void *)&IRRunMemCheck, Imm32(checkedPC), R(SCRATCH1));184TEST(32, R(EAX), R(EAX));185J_CC(CC_NZ, dispatcherCheckCoreState_, true);186187SetJumpTarget(noHits);188}189break;190191default:192INVALIDOP;193break;194}195}196197void X64JitBackend::CompIR_System(IRInst inst) {198CONDITIONAL_DISABLE;199200switch (inst.op) {201case IROp::Syscall:202FlushAll();203SaveStaticRegisters();204205WriteDebugProfilerStatus(IRProfilerStatus::SYSCALL);206#ifdef USE_PROFILER207// When profiling, we can't skip CallSyscall, since it times syscalls.208ABI_CallFunctionC((const u8 *)&CallSyscall, inst.constant);209#else210// Skip the CallSyscall where possible.211{212MIPSOpcode op(inst.constant);213void *quickFunc = GetQuickSyscallFunc(op);214if (quickFunc) {215ABI_CallFunctionP((const u8 *)quickFunc, (void *)GetSyscallFuncPointer(op));216} else {217ABI_CallFunctionC((const u8 *)&CallSyscall, inst.constant);218}219}220#endif221222WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);223LoadStaticRegisters();224// This is always followed by an ExitToPC, where we check coreState.225break;226227case IROp::CallReplacement:228FlushAll();229SaveStaticRegisters();230WriteDebugProfilerStatus(IRProfilerStatus::REPLACEMENT);231ABI_CallFunction(GetReplacementFunc(inst.constant)->replaceFunc);232WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);233LoadStaticRegisters();234235// Since we flushed above, and we're mapping write, EAX should be safe.236regs_.Map(inst);237MOV(32, regs_.R(inst.dest), R(EAX));238NEG(32, R(EAX));239// Set it back if it negate made it negative. That's the absolute value.240CMOVcc(32, EAX, regs_.R(inst.dest), CC_S);241242// Now set the dest to the sign bit status.243SAR(32, regs_.R(inst.dest), Imm8(31));244245if (jo.downcountInRegister)246SUB(32, R(DOWNCOUNTREG), R(EAX));247else248SUB(32, MDisp(CTXREG, downcountOffset), R(EAX));249break;250251case IROp::Break:252FlushAll();253// This doesn't naturally have restore/apply around it.254RestoreRoundingMode(true);255SaveStaticRegisters();256MovFromPC(SCRATCH1);257ABI_CallFunctionR((const void *)&Core_Break, SCRATCH1);258LoadStaticRegisters();259ApplyRoundingMode(true);260MovFromPC(SCRATCH1);261LEA(32, SCRATCH1, MDisp(SCRATCH1, 4));262JMP(dispatcherPCInSCRATCH1_, true);263break;264265default:266INVALIDOP;267break;268}269}270271void X64JitBackend::CompIR_Transfer(IRInst inst) {272CONDITIONAL_DISABLE;273274switch (inst.op) {275case IROp::SetCtrlVFPU:276regs_.SetGPRImm(IRREG_VFPU_CTRL_BASE + inst.dest, (int32_t)inst.constant);277break;278279case IROp::SetCtrlVFPUReg:280regs_.Map(inst);281MOV(32, regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.R(inst.src1));282break;283284case IROp::SetCtrlVFPUFReg:285regs_.Map(inst);286MOVD_xmm(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.FX(inst.src1));287break;288289case IROp::FpCondFromReg:290regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });291MOV(32, regs_.R(IRREG_FPCOND), regs_.R(inst.src1));292break;293294case IROp::FpCondToReg:295regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });296MOV(32, regs_.R(inst.dest), regs_.R(IRREG_FPCOND));297break;298299case IROp::FpCtrlFromReg:300regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });301// Mask out the unused bits, and store fcr31 (using fpcond as a temp.)302MOV(32, regs_.R(IRREG_FPCOND), Imm32(0x0181FFFF));303AND(32, regs_.R(IRREG_FPCOND), regs_.R(inst.src1));304MOV(32, MDisp(CTXREG, fcr31Offset), regs_.R(IRREG_FPCOND));305306// With that done, grab bit 23, the actual fpcond.307SHR(32, regs_.R(IRREG_FPCOND), Imm8(23));308AND(32, regs_.R(IRREG_FPCOND), Imm32(1));309break;310311case IROp::FpCtrlToReg:312regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });313// Start by clearing the fpcond bit (might as well mask while we're here.)314MOV(32, regs_.R(inst.dest), Imm32(0x0101FFFF));315AND(32, regs_.R(inst.dest), MDisp(CTXREG, fcr31Offset));316317AND(32, regs_.R(IRREG_FPCOND), Imm32(1));318if (cpu_info.bBMI2) {319RORX(32, SCRATCH1, regs_.R(IRREG_FPCOND), 32 - 23);320} else {321MOV(32, R(SCRATCH1), regs_.R(IRREG_FPCOND));322SHL(32, R(SCRATCH1), Imm8(23));323}324OR(32, regs_.R(inst.dest), R(SCRATCH1));325326// Update fcr31 while we were here, for consistency.327MOV(32, MDisp(CTXREG, fcr31Offset), regs_.R(inst.dest));328break;329330case IROp::VfpuCtrlToReg:331regs_.Map(inst);332MOV(32, regs_.R(inst.dest), regs_.R(IRREG_VFPU_CTRL_BASE + inst.src1));333break;334335case IROp::FMovFromGPR:336if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) {337regs_.MapFPR(inst.dest, MIPSMap::NOINIT);338XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));339} else {340regs_.Map(inst);341MOVD_xmm(regs_.FX(inst.dest), regs_.R(inst.src1));342}343break;344345case IROp::FMovToGPR:346regs_.Map(inst);347MOVD_xmm(regs_.R(inst.dest), regs_.FX(inst.src1));348break;349350default:351INVALIDOP;352break;353}354}355356void X64JitBackend::CompIR_ValidateAddress(IRInst inst) {357CONDITIONAL_DISABLE;358359bool isWrite = inst.src2 & 1;360int alignment = 0;361switch (inst.op) {362case IROp::ValidateAddress8:363alignment = 1;364break;365366case IROp::ValidateAddress16:367alignment = 2;368break;369370case IROp::ValidateAddress32:371alignment = 4;372break;373374case IROp::ValidateAddress128:375alignment = 16;376break;377378default:379INVALIDOP;380break;381}382383if (regs_.IsGPRMappedAsPointer(inst.src1)) {384LEA(PTRBITS, SCRATCH1, MDisp(regs_.RXPtr(inst.src1), inst.constant));385#if defined(MASKED_PSP_MEMORY)386SUB(PTRBITS, R(SCRATCH1), ImmPtr(Memory::base));387#else388SUB(PTRBITS, R(SCRATCH1), R(MEMBASEREG));389#endif390} else {391regs_.Map(inst);392LEA(PTRBITS, SCRATCH1, MDisp(regs_.RX(inst.src1), inst.constant));393}394AND(32, R(SCRATCH1), Imm32(0x3FFFFFFF));395396std::vector<FixupBranch> validJumps;397398FixupBranch unaligned;399if (alignment != 1) {400TEST(32, R(SCRATCH1), Imm32(alignment - 1));401unaligned = J_CC(CC_NZ);402}403404CMP(32, R(SCRATCH1), Imm32(PSP_GetUserMemoryEnd() - alignment));405FixupBranch tooHighRAM = J_CC(CC_A);406CMP(32, R(SCRATCH1), Imm32(PSP_GetKernelMemoryBase()));407validJumps.push_back(J_CC(CC_AE, true));408409CMP(32, R(SCRATCH1), Imm32(PSP_GetVidMemEnd() - alignment));410FixupBranch tooHighVid = J_CC(CC_A);411CMP(32, R(SCRATCH1), Imm32(PSP_GetVidMemBase()));412validJumps.push_back(J_CC(CC_AE, true));413414CMP(32, R(SCRATCH1), Imm32(PSP_GetScratchpadMemoryEnd() - alignment));415FixupBranch tooHighScratch = J_CC(CC_A);416CMP(32, R(SCRATCH1), Imm32(PSP_GetScratchpadMemoryBase()));417validJumps.push_back(J_CC(CC_AE, true));418419if (alignment != 1)420SetJumpTarget(unaligned);421SetJumpTarget(tooHighRAM);422SetJumpTarget(tooHighVid);423SetJumpTarget(tooHighScratch);424425// If we got here, something unusual and bad happened, so we'll always go back to the dispatcher.426// Because of that, we can avoid flushing outside this case.427auto regsCopy = regs_;428regsCopy.FlushAll();429430// Ignores the return value, always returns to the dispatcher.431// Otherwise would need a thunk to restore regs.432ABI_CallFunctionACC((const void *)&ReportBadAddress, R(SCRATCH1), alignment, isWrite);433JMP(dispatcherCheckCoreState_, true);434435for (FixupBranch &b : validJumps)436SetJumpTarget(b);437}438439} // namespace MIPSComp440441#endif442443444