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GitHub Repository: hrydgard/ppsspp
Path: blob/master/ext/riscv-disas.cpp
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/*
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 * RISC-V Disassembler
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 *
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 * Copyright (c) 2016-2017 Michael Clark <[email protected]>
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 * Copyright (c) 2017-2018 SiFive, Inc.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#define __STDC_FORMAT_MACROS 1
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#include <cstdlib>
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#include <cstdio>
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#include <cmath>
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#include <cinttypes>
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#include "riscv-disas.h"
32

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typedef struct {
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    const int op;
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    const rvc_constraint *constraints;
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} rv_comp_data;
37

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enum {
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    rvcd_imm_nz = 0x1,
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    rvcd_imm_nz_hint = 0x2
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};
42

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typedef struct {
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    const char * const name;
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    const rv_codec codec;
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    const char * const format;
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    const rv_comp_data *pseudo;
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    const short decomp_rv32;
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    const short decomp_rv64;
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    const short decomp_rv128;
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    const short decomp_data;
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} rv_opcode_data;
53

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/* register names */
55

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static const char rv_ireg_name_sym[32][5] = {
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    "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
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    "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
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    "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
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    "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
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};
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static const char rv_freg_name_sym[32][5] = {
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    "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
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    "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
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    "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
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    "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
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};
69

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/* instruction formats */
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static const char rv_fmt_none[]                   = "O\t";
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static const char rv_fmt_rs1[]                    = "O\t1";
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static const char rv_fmt_offset[]                 = "O\to";
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static const char rv_fmt_pred_succ[]              = "O\tp,s";
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static const char rv_fmt_rs1_rs2[]                = "O\t1,2";
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static const char rv_fmt_rd_imm[]                 = "O\t0,i";
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static const char rv_fmt_rd_offset[]              = "O\t0,o";
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static const char rv_fmt_rd_rs1_rs2[]             = "O\t0,1,2";
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static const char rv_fmt_frd_rs1[]                = "O\t3,1";
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static const char rv_fmt_rd_frs1[]                = "O\t0,4";
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static const char rv_fmt_rd_frs1_frs2[]           = "O\t0,4,5";
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static const char rv_fmt_frd_frs1[]               = "O\t3,4";
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static const char rv_fmt_frd_frs1_frs2[]          = "O\t3,4,5";
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static const char rv_fmt_rm_frd_frs1[]            = "O\tr,3,4";
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static const char rv_fmt_rm_frd_rs1[]             = "O\tr,3,1";
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static const char rv_fmt_rm_rd_frs1[]             = "O\tr,0,4";
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static const char rv_fmt_rm_frd_frs1_frs2[]       = "O\tr,3,4,5";
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static const char rv_fmt_rm_frd_frs1_frs2_frs3[]  = "O\tr,3,4,5,6";
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static const char rv_fmt_rd_rs1_imm[]             = "O\t0,1,i";
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static const char rv_fmt_rd_rs1_offset[]          = "O\t0,1,i";
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static const char rv_fmt_rd_offset_rs1[]          = "O\t0,i(1)";
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static const char rv_fmt_frd_offset_rs1[]         = "O\t3,i(1)";
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static const char rv_fmt_rd_csr_rs1[]             = "O\t0,c,1";
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static const char rv_fmt_rd_csr_zimm[]            = "O\t0,c,7";
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static const char rv_fmt_rs2_offset_rs1[]         = "O\t2,i(1)";
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static const char rv_fmt_frs2_offset_rs1[]        = "O\t5,i(1)";
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static const char rv_fmt_rs1_rs2_offset[]         = "O\t1,2,o";
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static const char rv_fmt_rs2_rs1_offset[]         = "O\t2,1,o";
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static const char rv_fmt_aqrl_rd_rs2_rs1[]        = "OAR\t0,2,(1)";
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static const char rv_fmt_aqrl_rd_rs1[]            = "OAR\t0,(1)";
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static const char rv_fmt_rd[]                     = "O\t0";
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static const char rv_fmt_rd_zimm[]                = "O\t0,7";
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static const char rv_fmt_rd_rs1[]                 = "O\t0,1";
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static const char rv_fmt_rd_rs2[]                 = "O\t0,2";
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static const char rv_fmt_rs1_offset[]             = "O\t1,o";
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static const char rv_fmt_rs2_offset[]             = "O\t2,o";
108

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/* pseudo-instruction constraints */
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static const rvc_constraint rvcc_last[] = { rvc_end };
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static const rvc_constraint rvcc_imm_eq_zero[] = { rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_imm_eq_n1[] = { rvc_imm_eq_n1, rvc_end };
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static const rvc_constraint rvcc_imm_eq_p1[] = { rvc_imm_eq_p1, rvc_end };
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static const rvc_constraint rvcc_rs1_eq_x0[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_rs2_eq_x0[] = { rvc_rs2_eq_x0, rvc_end };
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static const rvc_constraint rvcc_rs2_eq_rs1[] = { rvc_rs2_eq_rs1, rvc_end };
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static const rvc_constraint rvcc_jal_j[] = { rvc_rd_eq_x0, rvc_end };
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static const rvc_constraint rvcc_jal_jal[] = { rvc_rd_eq_ra, rvc_end };
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static const rvc_constraint rvcc_jalr_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_jalr_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_jalr_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_addi_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
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static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
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static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
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static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
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static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
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static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc82, rvc_end };
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static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
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static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
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static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
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static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
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static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
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static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
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static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
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static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
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/* pseudo-instruction metadata */
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static const rv_comp_data rvcp_jal[] = {
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    { rv_op_j, rvcc_jal_j },
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    { rv_op_jal, rvcc_jal_jal },
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    { rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_jalr[] = {
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    { rv_op_ret, rvcc_jalr_ret },
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    { rv_op_jr, rvcc_jalr_jr },
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    { rv_op_jalr, rvcc_jalr_jalr },
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    { rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_beq[] = {
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    { rv_op_beqz, rvcc_rs2_eq_x0 },
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    { rv_op_illegal, NULL }
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};
158

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static const rv_comp_data rvcp_bne[] = {
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    { rv_op_bnez, rvcc_rs2_eq_x0 },
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    { rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_blt[] = {
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    { rv_op_bltz, rvcc_rs2_eq_x0 },
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    { rv_op_bgtz, rvcc_rs1_eq_x0 },
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    { rv_op_bgt, rvcc_last },
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    { rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_bge[] = {
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    { rv_op_bgez, rvcc_rs2_eq_x0 },
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    { rv_op_blez, rvcc_rs1_eq_x0 },
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    { rv_op_ble, rvcc_last },
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    { rv_op_illegal, NULL }
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};
177

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static const rv_comp_data rvcp_bltu[] = {
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    { rv_op_bgtu, rvcc_last },
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    { rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_bgeu[] = {
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    { rv_op_bleu, rvcc_last },
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    { rv_op_illegal, NULL }
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};
187

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static const rv_comp_data rvcp_addi[] = {
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    { rv_op_nop, rvcc_addi_nop },
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    { rv_op_mv, rvcc_imm_eq_zero },
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    { rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_sltiu[] = {
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    { rv_op_seqz, rvcc_imm_eq_p1 },
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    { rv_op_illegal, NULL }
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};
198

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static const rv_comp_data rvcp_xori[] = {
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    { rv_op_not, rvcc_imm_eq_n1 },
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    { rv_op_illegal, NULL }
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};
203

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static const rv_comp_data rvcp_sub[] = {
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    { rv_op_neg, rvcc_rs1_eq_x0 },
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    { rv_op_illegal, NULL }
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};
208

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static const rv_comp_data rvcp_slt[] = {
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    { rv_op_sltz, rvcc_rs2_eq_x0 },
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    { rv_op_sgtz, rvcc_rs1_eq_x0 },
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    { rv_op_illegal, NULL }
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};
214

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static const rv_comp_data rvcp_sltu[] = {
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    { rv_op_snez, rvcc_rs1_eq_x0 },
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    { rv_op_illegal, NULL }
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};
219

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static const rv_comp_data rvcp_addiw[] = {
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    { rv_op_sext_w, rvcc_imm_eq_zero },
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    { rv_op_illegal, NULL }
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};
224

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static const rv_comp_data rvcp_subw[] = {
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    { rv_op_negw, rvcc_rs1_eq_x0 },
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    { rv_op_illegal, NULL }
228
};
229

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static const rv_comp_data rvcp_csrrw[] = {
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    { rv_op_fscsr, rvcc_fscsr },
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    { rv_op_fsrm, rvcc_fsrm },
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    { rv_op_fsflags, rvcc_fsflags },
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    { rv_op_illegal, NULL }
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};
236

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static const rv_comp_data rvcp_csrrs[] = {
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    { rv_op_rdcycle, rvcc_rdcycle },
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    { rv_op_rdtime, rvcc_rdtime },
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    { rv_op_rdinstret, rvcc_rdinstret },
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    { rv_op_rdcycleh, rvcc_rdcycleh },
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    { rv_op_rdtimeh, rvcc_rdtimeh },
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    { rv_op_rdinstreth, rvcc_rdinstreth },
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    { rv_op_frcsr, rvcc_frcsr },
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    { rv_op_frrm, rvcc_frrm },
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    { rv_op_frflags, rvcc_frflags },
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    { rv_op_illegal, NULL }
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};
249

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static const rv_comp_data rvcp_csrrwi[] = {
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    { rv_op_fsrmi, rvcc_fsrmi },
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    { rv_op_fsflagsi, rvcc_fsflagsi },
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    { rv_op_illegal, NULL }
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};
255

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static const rv_comp_data rvcp_fsgnj_h[] = {
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    { rv_op_fmv_h, rvcc_rs2_eq_rs1 },
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    { rv_op_illegal, NULL }
259
};
260

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static const rv_comp_data rvcp_fsgnjn_h[] = {
262
    { rv_op_fneg_h, rvcc_rs2_eq_rs1 },
263
    { rv_op_illegal, NULL }
264
};
265

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static const rv_comp_data rvcp_fsgnjx_h[] = {
267
    { rv_op_fabs_h, rvcc_rs2_eq_rs1 },
268
    { rv_op_illegal, NULL }
269
};
270

271
static const rv_comp_data rvcp_fsgnj_s[] = {
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    { rv_op_fmv_s, rvcc_rs2_eq_rs1 },
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    { rv_op_illegal, NULL }
274
};
275

276
static const rv_comp_data rvcp_fsgnjn_s[] = {
277
    { rv_op_fneg_s, rvcc_rs2_eq_rs1 },
278
    { rv_op_illegal, NULL }
279
};
280

281
static const rv_comp_data rvcp_fsgnjx_s[] = {
282
    { rv_op_fabs_s, rvcc_rs2_eq_rs1 },
283
    { rv_op_illegal, NULL }
284
};
285

286
static const rv_comp_data rvcp_fsgnj_d[] = {
287
    { rv_op_fmv_d, rvcc_rs2_eq_rs1 },
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    { rv_op_illegal, NULL }
289
};
290

291
static const rv_comp_data rvcp_fsgnjn_d[] = {
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    { rv_op_fneg_d, rvcc_rs2_eq_rs1 },
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    { rv_op_illegal, NULL }
294
};
295

296
static const rv_comp_data rvcp_fsgnjx_d[] = {
297
    { rv_op_fabs_d, rvcc_rs2_eq_rs1 },
298
    { rv_op_illegal, NULL }
299
};
300

301
static const rv_comp_data rvcp_fsgnj_q[] = {
302
    { rv_op_fmv_q, rvcc_rs2_eq_rs1 },
303
    { rv_op_illegal, NULL }
304
};
305

306
static const rv_comp_data rvcp_fsgnjn_q[] = {
307
    { rv_op_fneg_q, rvcc_rs2_eq_rs1 },
308
    { rv_op_illegal, NULL }
309
};
310

311
static const rv_comp_data rvcp_fsgnjx_q[] = {
312
    { rv_op_fabs_q, rvcc_rs2_eq_rs1 },
313
    { rv_op_illegal, NULL }
314
};
315

316
/* instruction metadata */
317

318
const rv_opcode_data opcode_data[] = {
319
    { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
320
    { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
321
    { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
322
    { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
323
    { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
324
    { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
325
    { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
326
    { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
327
    { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
328
    { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
329
    { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
330
    { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
331
    { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
332
    { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
333
    { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
334
    { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
335
    { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
336
    { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
337
    { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
338
    { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
339
    { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
340
    { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
341
    { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
342
    { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
343
    { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
344
    { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
345
    { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
346
    { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
347
    { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
348
    { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
349
    { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
350
    { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
351
    { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
352
    { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
353
    { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
354
    { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
355
    { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
356
    { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
357
    { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
358
    { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
359
    { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
360
    { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
361
    { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
362
    { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
363
    { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
364
    { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
365
    { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
366
    { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
367
    { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
368
    { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
369
    { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
370
    { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
371
    { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
372
    { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
373
    { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
374
    { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
375
    { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
376
    { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
377
    { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
378
    { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
379
    { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
380
    { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
381
    { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
382
    { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
383
    { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
384
    { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
385
    { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
386
    { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
387
    { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
388
    { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
389
    { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
390
    { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
391
    { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
392
    { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
393
    { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
394
    { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
395
    { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
396
    { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
397
    { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
398
    { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
399
    { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
400
    { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
401
    { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
402
    { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
403
    { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
404
    { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
405
    { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
406
    { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
407
    { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
408
    { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
409
    { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
410
    { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
411
    { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
412
    { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
413
    { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
414
    { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
415
    { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
416
    { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
417
    { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
418
    { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
419
    { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
420
    { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
421
    { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
422
    { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
423
    { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
424
    { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
425
    { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
426
    { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
427
    { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
428
    { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
429
    { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
430
    { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
431
    { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
432
    { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
433
    { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
434
    { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
435
    { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
436
    { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
437
    { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
438
    { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
439
    { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
440
    { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
441
    { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
442
    { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
443
    { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
444
    { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
445
    { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
446
    { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
447
    { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
448
    { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
449
    { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
450
    { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
451
    { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
452
    { "fmadd.h", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
453
    { "fmsub.h", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
454
    { "fnmsub.h", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
455
    { "fnmadd.h", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
456
    { "fadd.h", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
457
    { "fsub.h", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
458
    { "fmul.h", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
459
    { "fdiv.h", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
460
    { "fsgnj.h", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_h, 0, 0, 0 },
461
    { "fsgnjn.h", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_h, 0, 0, 0 },
462
    { "fsgnjx.h", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_h, 0, 0, 0 },
463
    { "fmin.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
464
    { "fmax.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
465
    { "fsqrt.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
466
    { "fle.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
467
    { "flt.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
468
    { "feq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
469
    { "fcvt.w.h", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
470
    { "fcvt.wu.h", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
471
    { "fcvt.h.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
472
    { "fcvt.h.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
473
    { "fclass.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
474
    { "fcvt.l.h", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
475
    { "fcvt.lu.h", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
476
    { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
477
    { "fcvt.h.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
478
    { "fcvt.h.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
479
    { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
480
    { "fcvt.s.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
481
    { "fcvt.h.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
482
    { "fcvt.d.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
483
    { "fcvt.h.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
484
    { "fcvt.q.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
485
    { "fcvt.h.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
486
    { "fmv.h", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
487
    { "fabs.h", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
488
    { "fneg.h", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
489
    { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
490
    { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
491
    { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
492
    { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
493
    { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
494
    { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
495
    { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
496
    { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
497
    { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
498
    { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
499
    { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
500
    { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
501
    { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
502
    { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
503
    { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
504
    { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
505
    { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
506
    { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
507
    { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
508
    { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
509
    { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
510
    { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
511
    { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
512
    { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
513
    { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
514
    { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
515
    { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
516
    { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
517
    { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
518
    { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
519
    { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
520
    { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
521
    { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
522
    { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
523
    { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
524
    { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
525
    { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
526
    { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
527
    { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
528
    { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
529
    { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
530
    { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
531
    { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
532
    { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
533
    { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
534
    { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
535
    { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
536
    { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
537
    { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
538
    { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
539
    { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
540
    { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
541
    { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
542
    { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
543
    { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
544
    { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
545
    { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
546
    { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
547
    { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
548
    { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
549
    { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
550
    { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
551
    { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
552
    { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
553
    { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
554
    { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
555
    { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
556
    { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
557
    { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
558
    { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
559
    { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
560
    { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
561
    { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
562
    { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
563
    { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
564
    { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
565
    { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
566
    { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
567
    { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
568
    { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
569
    { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
570
    { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
571
    { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
572
    { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
573
    { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
574
    { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
575
    { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
576
    { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
577
    { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
578
    { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
579
    { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
580
    { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
581
    { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
582
    { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
583
    { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
584
    { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
585
    { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
586
    { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
587
    { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
588
    { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
589
    { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
590
    { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
591
    { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
592
    { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
593
    { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz_hint },
594
    { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
595
    { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
596
    { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
597
    { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz },
598
    { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz },
599
    { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz },
600
    { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi, rvcd_imm_nz },
601
    { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
602
    { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
603
    { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
604
    { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
605
    { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
606
    { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
607
    { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
608
    { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
609
    { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
610
    { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli, rvcd_imm_nz },
611
    { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
612
    { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
613
    { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
614
    { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
615
    { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
616
    { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
617
    { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
618
    { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
619
    { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
620
    { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
621
    { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
622
    { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
623
    { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
624
    { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
625
    { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
626
    { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
627
    { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
628
    { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
629
    { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
630
    { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
631
    { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
632
    { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
633
    { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
634
    { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
635
    { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
636
    { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
637
    { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
638
    { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
639
    { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
640
    { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
641
    { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
642
    { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
643
    { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
644
    { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
645
    { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
646
    { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
647
    { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
648
    { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
649
    { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
650
    { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
651
    { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
652
    { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
653
    { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
654
    { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
655
    { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
656
    { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
657
    { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
658
    { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
659
    { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
660
    { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
661
    { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
662
    { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
663
    { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
664
    { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
665
    { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
666
    { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
667
    { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
668
    { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
669
    { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
670
    { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
671
    { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
672
    { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
673
    { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
674
    { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
675
    { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
676
    { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
677
    { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
678
    { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
679
    { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
680
    { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
681
    { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
682
    { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
683
    { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
684
    { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
685
    { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
686
    { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
687
    { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
688
    { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
689
    { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
690
    { "clz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
691
    { "clzw", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
692
    { "cpop", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
693
    { "cpopw", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
694
    { "ctz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
695
    { "ctzw", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
696
    { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
697
    { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
698
    { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
699
    { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
700
    { "orc.b", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
701
    { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
702
    { "rev8", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
703
    { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
704
    { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
705
    { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
706
    { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
707
    { "roriw", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
708
    { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
709
    { "sext.b", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
710
    { "sext.h", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
711
    { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
712
    { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
713
    { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
714
    { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
715
    { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
716
    { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
717
    { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
718
    { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
719
    { "zext.h", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
720
};
721

722
/* CSR names */
723

724
static const char *csr_name(int csrno)
725
{
726
    switch (csrno) {
727
    case 0x0000: return "ustatus";
728
    case 0x0001: return "fflags";
729
    case 0x0002: return "frm";
730
    case 0x0003: return "fcsr";
731
    case 0x0004: return "uie";
732
    case 0x0005: return "utvec";
733
    case 0x0007: return "utvt";
734
    case 0x0008: return "vstart";
735
    case 0x0009: return "vxsat";
736
    case 0x000a: return "vxrm";
737
    case 0x000f: return "vcsr";
738
    case 0x0040: return "uscratch";
739
    case 0x0041: return "uepc";
740
    case 0x0042: return "ucause";
741
    case 0x0043: return "utval";
742
    case 0x0044: return "uip";
743
    case 0x0045: return "unxti";
744
    case 0x0046: return "uintstatus";
745
    case 0x0048: return "uscratchcsw";
746
    case 0x0049: return "uscratchcswl";
747
    case 0x0100: return "sstatus";
748
    case 0x0102: return "sedeleg";
749
    case 0x0103: return "sideleg";
750
    case 0x0104: return "sie";
751
    case 0x0105: return "stvec";
752
    case 0x0106: return "scounteren";
753
    case 0x0107: return "stvt";
754
    case 0x0140: return "sscratch";
755
    case 0x0141: return "sepc";
756
    case 0x0142: return "scause";
757
    case 0x0143: return "stval";
758
    case 0x0144: return "sip";
759
    case 0x0145: return "snxti";
760
    case 0x0146: return "sintstatus";
761
    case 0x0148: return "sscratchcsw";
762
    case 0x0149: return "sscratchcswl";
763
    case 0x0180: return "satp";
764
    case 0x0200: return "vsstatus";
765
    case 0x0204: return "vsie";
766
    case 0x0205: return "vstvec";
767
    case 0x0240: return "vsscratch";
768
    case 0x0241: return "vsepc";
769
    case 0x0242: return "vscause";
770
    case 0x0243: return "vstval";
771
    case 0x0244: return "vsip";
772
    case 0x0280: return "vsatp";
773
    case 0x0300: return "mstatus";
774
    case 0x0301: return "misa";
775
    case 0x0302: return "medeleg";
776
    case 0x0303: return "mideleg";
777
    case 0x0304: return "mie";
778
    case 0x0305: return "mtvec";
779
    case 0x0306: return "mcounteren";
780
    case 0x0307: return "mtvt";
781
    case 0x0310: return "mstatush";
782
    case 0x0320: return "mcountinhibit";
783
    case 0x0323: return "mhpmevent3";
784
    case 0x0324: return "mhpmevent4";
785
    case 0x0325: return "mhpmevent5";
786
    case 0x0326: return "mhpmevent6";
787
    case 0x0327: return "mhpmevent7";
788
    case 0x0328: return "mhpmevent8";
789
    case 0x0329: return "mhpmevent9";
790
    case 0x032a: return "mhpmevent10";
791
    case 0x032b: return "mhpmevent11";
792
    case 0x032c: return "mhpmevent12";
793
    case 0x032d: return "mhpmevent13";
794
    case 0x032e: return "mhpmevent14";
795
    case 0x032f: return "mhpmevent15";
796
    case 0x0330: return "mhpmevent16";
797
    case 0x0331: return "mhpmevent17";
798
    case 0x0332: return "mhpmevent18";
799
    case 0x0333: return "mhpmevent19";
800
    case 0x0334: return "mhpmevent20";
801
    case 0x0335: return "mhpmevent21";
802
    case 0x0336: return "mhpmevent22";
803
    case 0x0337: return "mhpmevent23";
804
    case 0x0338: return "mhpmevent24";
805
    case 0x0339: return "mhpmevent25";
806
    case 0x033a: return "mhpmevent26";
807
    case 0x033b: return "mhpmevent27";
808
    case 0x033c: return "mhpmevent28";
809
    case 0x033d: return "mhpmevent29";
810
    case 0x033e: return "mhpmevent30";
811
    case 0x033f: return "mhpmevent31";
812
    case 0x0340: return "mscratch";
813
    case 0x0341: return "mepc";
814
    case 0x0342: return "mcause";
815
    case 0x0343: return "mtval";
816
    case 0x0344: return "mip";
817
    case 0x0345: return "mnxti";
818
    case 0x0346: return "mintstatus";
819
    case 0x0348: return "mscratchcsw";
820
    case 0x0349: return "mscratchcswl";
821
    case 0x034a: return "mtinst";
822
    case 0x034b: return "mtval2";
823
    case 0x03a0: return "pmpcfg0";
824
    case 0x03a1: return "pmpcfg1";
825
    case 0x03a2: return "pmpcfg2";
826
    case 0x03a3: return "pmpcfg3";
827
    case 0x03b0: return "pmpaddr0";
828
    case 0x03b1: return "pmpaddr1";
829
    case 0x03b2: return "pmpaddr2";
830
    case 0x03b3: return "pmpaddr3";
831
    case 0x03b4: return "pmpaddr4";
832
    case 0x03b5: return "pmpaddr5";
833
    case 0x03b6: return "pmpaddr6";
834
    case 0x03b7: return "pmpaddr7";
835
    case 0x03b8: return "pmpaddr8";
836
    case 0x03b9: return "pmpaddr9";
837
    case 0x03ba: return "pmpaddr10";
838
    case 0x03bb: return "pmpaddr11";
839
    case 0x03bc: return "pmpaddr12";
840
    case 0x03bd: return "pmpaddr13";
841
    case 0x03be: return "pmpaddr14";
842
    case 0x03bf: return "pmpaddr15";
843
    case 0x0600: return "hstatus";
844
    case 0x0602: return "hedeleg";
845
    case 0x0603: return "hideleg";
846
    case 0x0604: return "hie";
847
    case 0x0605: return "htimedelta";
848
    case 0x0606: return "hcounteren";
849
    case 0x0607: return "hgeie";
850
    case 0x0615: return "htimedeltah";
851
    case 0x0643: return "htval";
852
    case 0x0644: return "hip";
853
    case 0x0645: return "hvip";
854
    case 0x064a: return "htinst";
855
    case 0x0680: return "hgatp";
856
    case 0x07a0: return "tselect";
857
    case 0x07a1: return "tdata1";
858
    case 0x07a2: return "tdata2";
859
    case 0x07a3: return "tdata3";
860
    case 0x07a4: return "tinfo";
861
    case 0x07a5: return "tcontrol";
862
    case 0x07a8: return "mcontext";
863
    case 0x07a9: return "mnoise";
864
    case 0x07aa: return "scontext";
865
    case 0x07b0: return "dcsr";
866
    case 0x07b1: return "dpc";
867
    case 0x07b2: return "dscratch0";
868
    case 0x07b3: return "dscratch1";
869
    case 0x0b00: return "mcycle";
870
    case 0x0b02: return "minstret";
871
    case 0x0b03: return "mhpmcounter3";
872
    case 0x0b04: return "mhpmcounter4";
873
    case 0x0b05: return "mhpmcounter5";
874
    case 0x0b06: return "mhpmcounter6";
875
    case 0x0b07: return "mhpmcounter7";
876
    case 0x0b08: return "mhpmcounter8";
877
    case 0x0b09: return "mhpmcounter9";
878
    case 0x0b0a: return "mhpmcounter10";
879
    case 0x0b0b: return "mhpmcounter11";
880
    case 0x0b0c: return "mhpmcounter12";
881
    case 0x0b0d: return "mhpmcounter13";
882
    case 0x0b0e: return "mhpmcounter14";
883
    case 0x0b0f: return "mhpmcounter15";
884
    case 0x0b10: return "mhpmcounter16";
885
    case 0x0b11: return "mhpmcounter17";
886
    case 0x0b12: return "mhpmcounter18";
887
    case 0x0b13: return "mhpmcounter19";
888
    case 0x0b14: return "mhpmcounter20";
889
    case 0x0b15: return "mhpmcounter21";
890
    case 0x0b16: return "mhpmcounter22";
891
    case 0x0b17: return "mhpmcounter23";
892
    case 0x0b18: return "mhpmcounter24";
893
    case 0x0b19: return "mhpmcounter25";
894
    case 0x0b1a: return "mhpmcounter26";
895
    case 0x0b1b: return "mhpmcounter27";
896
    case 0x0b1c: return "mhpmcounter28";
897
    case 0x0b1d: return "mhpmcounter29";
898
    case 0x0b1e: return "mhpmcounter30";
899
    case 0x0b1f: return "mhpmcounter31";
900
    case 0x0b80: return "mcycleh";
901
    case 0x0b82: return "minstreth";
902
    case 0x0b83: return "mhpmcounter3h";
903
    case 0x0b84: return "mhpmcounter4h";
904
    case 0x0b85: return "mhpmcounter5h";
905
    case 0x0b86: return "mhpmcounter6h";
906
    case 0x0b87: return "mhpmcounter7h";
907
    case 0x0b88: return "mhpmcounter8h";
908
    case 0x0b89: return "mhpmcounter9h";
909
    case 0x0b8a: return "mhpmcounter10h";
910
    case 0x0b8b: return "mhpmcounter11h";
911
    case 0x0b8c: return "mhpmcounter12h";
912
    case 0x0b8d: return "mhpmcounter13h";
913
    case 0x0b8e: return "mhpmcounter14h";
914
    case 0x0b8f: return "mhpmcounter15h";
915
    case 0x0b90: return "mhpmcounter16h";
916
    case 0x0b91: return "mhpmcounter17h";
917
    case 0x0b92: return "mhpmcounter18h";
918
    case 0x0b93: return "mhpmcounter19h";
919
    case 0x0b94: return "mhpmcounter20h";
920
    case 0x0b95: return "mhpmcounter21h";
921
    case 0x0b96: return "mhpmcounter22h";
922
    case 0x0b97: return "mhpmcounter23h";
923
    case 0x0b98: return "mhpmcounter24h";
924
    case 0x0b99: return "mhpmcounter25h";
925
    case 0x0b9a: return "mhpmcounter26h";
926
    case 0x0b9b: return "mhpmcounter27h";
927
    case 0x0b9c: return "mhpmcounter28h";
928
    case 0x0b9d: return "mhpmcounter29h";
929
    case 0x0b9e: return "mhpmcounter30h";
930
    case 0x0b9f: return "mhpmcounter31h";
931
    case 0x0c00: return "cycle";
932
    case 0x0c01: return "time";
933
    case 0x0c02: return "instret";
934
    case 0x0c03: return "hpmcounter3";
935
    case 0x0c04: return "hpmcounter4";
936
    case 0x0c05: return "hpmcounter5";
937
    case 0x0c06: return "hpmcounter6";
938
    case 0x0c07: return "hpmcounter7";
939
    case 0x0c08: return "hpmcounter8";
940
    case 0x0c09: return "hpmcounter9";
941
    case 0x0c0a: return "hpmcounter10";
942
    case 0x0c0b: return "hpmcounter11";
943
    case 0x0c0c: return "hpmcounter12";
944
    case 0x0c0d: return "hpmcounter13";
945
    case 0x0c0e: return "hpmcounter14";
946
    case 0x0c0f: return "hpmcounter15";
947
    case 0x0c10: return "hpmcounter16";
948
    case 0x0c11: return "hpmcounter17";
949
    case 0x0c12: return "hpmcounter18";
950
    case 0x0c13: return "hpmcounter19";
951
    case 0x0c14: return "hpmcounter20";
952
    case 0x0c15: return "hpmcounter21";
953
    case 0x0c16: return "hpmcounter22";
954
    case 0x0c17: return "hpmcounter23";
955
    case 0x0c18: return "hpmcounter24";
956
    case 0x0c19: return "hpmcounter25";
957
    case 0x0c1a: return "hpmcounter26";
958
    case 0x0c1b: return "hpmcounter27";
959
    case 0x0c1c: return "hpmcounter28";
960
    case 0x0c1d: return "hpmcounter29";
961
    case 0x0c1e: return "hpmcounter30";
962
    case 0x0c1f: return "hpmcounter31";
963
    case 0x0c20: return "vl";
964
    case 0x0c21: return "vtype";
965
    case 0x0c22: return "vlenb";
966
    case 0x0c80: return "cycleh";
967
    case 0x0c81: return "timeh";
968
    case 0x0c82: return "instreth";
969
    case 0x0c83: return "hpmcounter3h";
970
    case 0x0c84: return "hpmcounter4h";
971
    case 0x0c85: return "hpmcounter5h";
972
    case 0x0c86: return "hpmcounter6h";
973
    case 0x0c87: return "hpmcounter7h";
974
    case 0x0c88: return "hpmcounter8h";
975
    case 0x0c89: return "hpmcounter9h";
976
    case 0x0c8a: return "hpmcounter10h";
977
    case 0x0c8b: return "hpmcounter11h";
978
    case 0x0c8c: return "hpmcounter12h";
979
    case 0x0c8d: return "hpmcounter13h";
980
    case 0x0c8e: return "hpmcounter14h";
981
    case 0x0c8f: return "hpmcounter15h";
982
    case 0x0c90: return "hpmcounter16h";
983
    case 0x0c91: return "hpmcounter17h";
984
    case 0x0c92: return "hpmcounter18h";
985
    case 0x0c93: return "hpmcounter19h";
986
    case 0x0c94: return "hpmcounter20h";
987
    case 0x0c95: return "hpmcounter21h";
988
    case 0x0c96: return "hpmcounter22h";
989
    case 0x0c97: return "hpmcounter23h";
990
    case 0x0c98: return "hpmcounter24h";
991
    case 0x0c99: return "hpmcounter25h";
992
    case 0x0c9a: return "hpmcounter26h";
993
    case 0x0c9b: return "hpmcounter27h";
994
    case 0x0c9c: return "hpmcounter28h";
995
    case 0x0c9d: return "hpmcounter29h";
996
    case 0x0c9e: return "hpmcounter30h";
997
    case 0x0c9f: return "hpmcounter31h";
998
    case 0x0e12: return "hgeip";
999
    case 0x0f11: return "mvendorid";
1000
    case 0x0f12: return "marchid";
1001
    case 0x0f13: return "mimpid";
1002
    case 0x0f14: return "mhartid";
1003
    case 0x0f15: return "mentropy";
1004
    default: return NULL;
1005
    }
1006
}
1007

1008
/* decode opcode */
1009

1010
static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
1011
{
1012
    rv_inst inst = dec->inst;
1013
    rv_opcode op = rv_op_illegal;
1014
    switch (((inst >> 0) & 0b11)) {
1015
    case 0:
1016
        switch (((inst >> 13) & 0b111)) {
1017
        case 0: op = rv_op_c_addi4spn; break;
1018
        case 1: op = (isa == rv128) ? rv_op_c_lq : rv_op_c_fld; break;
1019
        case 2: op = rv_op_c_lw; break;
1020
        case 3: op = (isa == rv32) ? rv_op_c_flw : rv_op_c_ld; break;
1021
        case 5: op = (isa == rv128) ? rv_op_c_sq : rv_op_c_fsd; break;
1022
        case 6: op = rv_op_c_sw; break;
1023
        case 7: op = (isa == rv32) ? rv_op_c_fsw : rv_op_c_sd; break;
1024
        }
1025
        break;
1026
    case 1:
1027
        switch (((inst >> 13) & 0b111)) {
1028
        case 0:
1029
            switch (((inst >> 2) & 0b11111111111)) {
1030
            case 0: op = rv_op_c_nop; break;
1031
            default: op = rv_op_c_addi; break;
1032
            }
1033
            break;
1034
        case 1: op = (isa == rv32) ? rv_op_c_jal : rv_op_c_addiw; break;
1035
        case 2: op = rv_op_c_li; break;
1036
        case 3:
1037
            switch (((inst >> 7) & 0b11111)) {
1038
            case 2: op = rv_op_c_addi16sp; break;
1039
            default: op = rv_op_c_lui; break;
1040
            }
1041
            break;
1042
        case 4:
1043
            switch (((inst >> 10) & 0b11)) {
1044
            case 0:
1045
                op = rv_op_c_srli;
1046
                break;
1047
            case 1:
1048
                op = rv_op_c_srai;
1049
                break;
1050
            case 2: op = rv_op_c_andi; break;
1051
            case 3:
1052
                switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
1053
                case 0: op = rv_op_c_sub; break;
1054
                case 1: op = rv_op_c_xor; break;
1055
                case 2: op = rv_op_c_or; break;
1056
                case 3: op = rv_op_c_and; break;
1057
                case 4: op = rv_op_c_subw; break;
1058
                case 5: op = rv_op_c_addw; break;
1059
                }
1060
                break;
1061
            }
1062
            break;
1063
        case 5: op = rv_op_c_j; break;
1064
        case 6: op = rv_op_c_beqz; break;
1065
        case 7: op = rv_op_c_bnez; break;
1066
        }
1067
        break;
1068
    case 2:
1069
        switch (((inst >> 13) & 0b111)) {
1070
        case 0:
1071
            op = rv_op_c_slli;
1072
            break;
1073
        case 1: op = (isa == rv128) ? rv_op_c_lqsp : rv_op_c_fldsp; break;
1074
        case 2: op = rv_op_c_lwsp; break;
1075
        case 3: op = (isa == rv32) ? rv_op_c_flwsp : rv_op_c_ldsp; break;
1076
        case 4:
1077
            switch (((inst >> 12) & 0b1)) {
1078
            case 0:
1079
                switch (((inst >> 2) & 0b11111)) {
1080
                case 0: op = rv_op_c_jr; break;
1081
                default: op = rv_op_c_mv; break;
1082
                }
1083
                break;
1084
            case 1:
1085
                switch (((inst >> 2) & 0b11111)) {
1086
                case 0:
1087
                    switch (((inst >> 7) & 0b11111)) {
1088
                    case 0: op = rv_op_c_ebreak; break;
1089
                    default: op = rv_op_c_jalr; break;
1090
                    }
1091
                    break;
1092
                default: op = rv_op_c_add; break;
1093
                }
1094
                break;
1095
            }
1096
            break;
1097
        case 5: op = (isa == rv128) ? rv_op_c_sqsp : rv_op_c_fsdsp; break;
1098
        case 6: op = rv_op_c_swsp; break;
1099
        case 7: op = (isa == rv32) ? rv_op_c_fswsp : rv_op_c_sdsp; break;
1100
        }
1101
        break;
1102
    case 3:
1103
        switch (((inst >> 2) & 0b11111)) {
1104
        case 0:
1105
            switch (((inst >> 12) & 0b111)) {
1106
            case 0: op = rv_op_lb; break;
1107
            case 1: op = rv_op_lh; break;
1108
            case 2: op = rv_op_lw; break;
1109
            case 3: op = rv_op_ld; break;
1110
            case 4: op = rv_op_lbu; break;
1111
            case 5: op = rv_op_lhu; break;
1112
            case 6: op = rv_op_lwu; break;
1113
            case 7: op = rv_op_ldu; break;
1114
            }
1115
            break;
1116
        case 1:
1117
            switch (((inst >> 12) & 0b111)) {
1118
            case 1: op = rv_op_flh; break;
1119
            case 2: op = rv_op_flw; break;
1120
            case 3: op = rv_op_fld; break;
1121
            case 4: op = rv_op_flq; break;
1122
            }
1123
            break;
1124
        case 3:
1125
            switch (((inst >> 12) & 0b111)) {
1126
            case 0: op = rv_op_fence; break;
1127
            case 1: op = rv_op_fence_i; break;
1128
            case 2: op = rv_op_lq; break;
1129
            }
1130
            break;
1131
        case 4:
1132
            switch (((inst >> 12) & 0b111)) {
1133
            case 0: op = rv_op_addi; break;
1134
            case 1:
1135
                switch (((inst >> 27) & 0b11111)) {
1136
                case 0: op = rv_op_slli; break;
1137
                case 5: op = rv_op_bseti; break;
1138
                case 9: op = rv_op_bclri; break;
1139
                case 12:
1140
                    switch (((inst >> 20) & 0b11111)) {
1141
                    case 0: op = rv_op_clz; break;
1142
                    case 1: op = rv_op_ctz; break;
1143
                    case 2: op = rv_op_cpop; break;
1144
                    case 4: op = rv_op_sext_b; break;
1145
                    case 5: op = rv_op_sext_h; break;
1146
                    }
1147
                    break;
1148
                case 13: op = rv_op_binvi; break;
1149
                }
1150
                break;
1151
            case 2: op = rv_op_slti; break;
1152
            case 3: op = rv_op_sltiu; break;
1153
            case 4: op = rv_op_xori; break;
1154
            case 5:
1155
                switch (((inst >> 27) & 0b11111)) {
1156
                case 0: op = rv_op_srli; break;
1157
                case 5:
1158
                    switch (((inst >> 20) & 0b1111111)) {
1159
                    case 7: op = rv_op_orc_b; break;
1160
                    }
1161
                    break;
1162
                case 8: op = rv_op_srai; break;
1163
                case 9: op = rv_op_bexti; break;
1164
                case 12: op = rv_op_rori; break;
1165
                case 13:
1166
                    switch (((inst >> 20) & 0b1111111)) {
1167
                    case 24: if (isa == rv32) op = rv_op_rev8; break;
1168
                    case 56: if (isa == rv64) op = rv_op_rev8; break;
1169
                    }
1170
                    break;
1171
                }
1172
                break;
1173
            case 6: op = rv_op_ori; break;
1174
            case 7: op = rv_op_andi; break;
1175
            }
1176
            break;
1177
        case 5: op = rv_op_auipc; break;
1178
        case 6:
1179
            switch (((inst >> 12) & 0b111)) {
1180
            case 0: op = rv_op_addiw; break;
1181
            case 1:
1182
                switch (((inst >> 25) & 0b1111111)) {
1183
                case 0: op = rv_op_slliw; break;
1184
                case 4: op = rv_op_slli_uw; break;
1185
                case 5: op = rv_op_slli_uw; break;
1186
                case 48:
1187
                    switch (((inst >> 20) & 0b11111)) {
1188
                    case 0: op = rv_op_clzw; break;
1189
                    case 1: op = rv_op_ctzw; break;
1190
                    case 2: op = rv_op_cpopw; break;
1191
                    }
1192
                    break;
1193
                }
1194
                break;
1195
            case 5:
1196
                switch (((inst >> 25) & 0b1111111)) {
1197
                case 0: op = rv_op_srliw; break;
1198
                case 32: op = rv_op_sraiw; break;
1199
                case 48: op = rv_op_roriw; break;
1200
                }
1201
                break;
1202
            }
1203
            break;
1204
        case 8:
1205
            switch (((inst >> 12) & 0b111)) {
1206
            case 0: op = rv_op_sb; break;
1207
            case 1: op = rv_op_sh; break;
1208
            case 2: op = rv_op_sw; break;
1209
            case 3: op = rv_op_sd; break;
1210
            case 4: op = rv_op_sq; break;
1211
            }
1212
            break;
1213
        case 9:
1214
            switch (((inst >> 12) & 0b111)) {
1215
            case 1: op = rv_op_fsh; break;
1216
            case 2: op = rv_op_fsw; break;
1217
            case 3: op = rv_op_fsd; break;
1218
            case 4: op = rv_op_fsq; break;
1219
            }
1220
            break;
1221
        case 11:
1222
            switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1223
            case 2: op = rv_op_amoadd_w; break;
1224
            case 3: op = rv_op_amoadd_d; break;
1225
            case 4: op = rv_op_amoadd_q; break;
1226
            case 10: op = rv_op_amoswap_w; break;
1227
            case 11: op = rv_op_amoswap_d; break;
1228
            case 12: op = rv_op_amoswap_q; break;
1229
            case 18:
1230
                switch (((inst >> 20) & 0b11111)) {
1231
                case 0: op = rv_op_lr_w; break;
1232
                }
1233
                break;
1234
            case 19:
1235
                switch (((inst >> 20) & 0b11111)) {
1236
                case 0: op = rv_op_lr_d; break;
1237
                }
1238
                break;
1239
            case 20:
1240
                switch (((inst >> 20) & 0b11111)) {
1241
                case 0: op = rv_op_lr_q; break;
1242
                }
1243
                break;
1244
            case 26: op = rv_op_sc_w; break;
1245
            case 27: op = rv_op_sc_d; break;
1246
            case 28: op = rv_op_sc_q; break;
1247
            case 34: op = rv_op_amoxor_w; break;
1248
            case 35: op = rv_op_amoxor_d; break;
1249
            case 36: op = rv_op_amoxor_q; break;
1250
            case 66: op = rv_op_amoor_w; break;
1251
            case 67: op = rv_op_amoor_d; break;
1252
            case 68: op = rv_op_amoor_q; break;
1253
            case 98: op = rv_op_amoand_w; break;
1254
            case 99: op = rv_op_amoand_d; break;
1255
            case 100: op = rv_op_amoand_q; break;
1256
            case 130: op = rv_op_amomin_w; break;
1257
            case 131: op = rv_op_amomin_d; break;
1258
            case 132: op = rv_op_amomin_q; break;
1259
            case 162: op = rv_op_amomax_w; break;
1260
            case 163: op = rv_op_amomax_d; break;
1261
            case 164: op = rv_op_amomax_q; break;
1262
            case 194: op = rv_op_amominu_w; break;
1263
            case 195: op = rv_op_amominu_d; break;
1264
            case 196: op = rv_op_amominu_q; break;
1265
            case 226: op = rv_op_amomaxu_w; break;
1266
            case 227: op = rv_op_amomaxu_d; break;
1267
            case 228: op = rv_op_amomaxu_q; break;
1268
            }
1269
            break;
1270
        case 12:
1271
            switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
1272
            case 0: op = rv_op_add; break;
1273
            case 1: op = rv_op_sll; break;
1274
            case 2: op = rv_op_slt; break;
1275
            case 3: op = rv_op_sltu; break;
1276
            case 4: op = rv_op_xor; break;
1277
            case 5: op = rv_op_srl; break;
1278
            case 6: op = rv_op_or; break;
1279
            case 7: op = rv_op_and; break;
1280
            case 8: op = rv_op_mul; break;
1281
            case 9: op = rv_op_mulh; break;
1282
            case 10: op = rv_op_mulhsu; break;
1283
            case 11: op = rv_op_mulhu; break;
1284
            case 12: op = rv_op_div; break;
1285
            case 13: op = rv_op_divu; break;
1286
            case 14: op = rv_op_rem; break;
1287
            case 15: op = rv_op_remu; break;
1288
            case 36:
1289
                switch (((inst >> 20) & 0b11111)) {
1290
                case 0: if (isa == rv32) op = rv_op_zext_h; break;
1291
                }
1292
                break;
1293
            case 41: op = rv_op_clmul; break;
1294
            case 42: op = rv_op_clmulr; break;
1295
            case 43: op = rv_op_clmulh; break;
1296
            case 44: op = rv_op_min; break;
1297
            case 45: op = rv_op_minu; break;
1298
            case 46: op = rv_op_max; break;
1299
            case 47: op = rv_op_maxu; break;
1300
            case 130: op = rv_op_sh1add; break;
1301
            case 132: op = rv_op_sh2add; break;
1302
            case 134: op = rv_op_sh3add; break;
1303
            case 161: op = rv_op_bset; break;
1304
            case 256: op = rv_op_sub; break;
1305
            case 260: op = rv_op_xnor; break;
1306
            case 261: op = rv_op_sra; break;
1307
            case 262: op = rv_op_orn; break;
1308
            case 263: op = rv_op_andn; break;
1309
            case 289: op = rv_op_bclr; break;
1310
            case 293: op = rv_op_bext; break;
1311
            case 385: op = rv_op_rol; break;
1312
            case 389: op = rv_op_ror; break;
1313
            case 417: op = rv_op_binv; break;
1314
            }
1315
            break;
1316
        case 13: op = rv_op_lui; break;
1317
        case 14:
1318
            switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
1319
            case 0: op = rv_op_addw; break;
1320
            case 1: op = rv_op_sllw; break;
1321
            case 5: op = rv_op_srlw; break;
1322
            case 8: op = rv_op_mulw; break;
1323
            case 12: op = rv_op_divw; break;
1324
            case 13: op = rv_op_divuw; break;
1325
            case 14: op = rv_op_remw; break;
1326
            case 15: op = rv_op_remuw; break;
1327
            case 32: op = rv_op_add_uw; break;
1328
            case 36:
1329
                switch (((inst >> 20) & 0b11111)) {
1330
                case 0: if (isa == rv64) op = rv_op_zext_h; break;
1331
                }
1332
                break;
1333
            case 130: op = rv_op_sh1add_uw; break;
1334
            case 132: op = rv_op_sh2add_uw; break;
1335
            case 134: op = rv_op_sh3add_uw; break;
1336
            case 256: op = rv_op_subw; break;
1337
            case 261: op = rv_op_sraw; break;
1338
            case 385: op = rv_op_rolw; break;
1339
            case 389: op = rv_op_rorw; break;
1340
            }
1341
            break;
1342
        case 16:
1343
            switch (((inst >> 25) & 0b11)) {
1344
            case 0: op = rv_op_fmadd_s; break;
1345
            case 1: op = rv_op_fmadd_d; break;
1346
            case 2: op = rv_op_fmadd_h; break;
1347
            case 3: op = rv_op_fmadd_q; break;
1348
            }
1349
            break;
1350
        case 17:
1351
            switch (((inst >> 25) & 0b11)) {
1352
            case 0: op = rv_op_fmsub_s; break;
1353
            case 1: op = rv_op_fmsub_d; break;
1354
            case 2: op = rv_op_fmsub_h; break;
1355
            case 3: op = rv_op_fmsub_q; break;
1356
            }
1357
            break;
1358
        case 18:
1359
            switch (((inst >> 25) & 0b11)) {
1360
            case 0: op = rv_op_fnmsub_s; break;
1361
            case 1: op = rv_op_fnmsub_d; break;
1362
            case 2: op = rv_op_fnmsub_h; break;
1363
            case 3: op = rv_op_fnmsub_q; break;
1364
            }
1365
            break;
1366
        case 19:
1367
            switch (((inst >> 25) & 0b11)) {
1368
            case 0: op = rv_op_fnmadd_s; break;
1369
            case 1: op = rv_op_fnmadd_d; break;
1370
            case 2: op = rv_op_fnmadd_h; break;
1371
            case 3: op = rv_op_fnmadd_q; break;
1372
            }
1373
            break;
1374
        case 20:
1375
            switch (((inst >> 25) & 0b1111111)) {
1376
            case 0: op = rv_op_fadd_s; break;
1377
            case 1: op = rv_op_fadd_d; break;
1378
            case 2: op = rv_op_fadd_h; break;
1379
            case 3: op = rv_op_fadd_q; break;
1380
            case 4: op = rv_op_fsub_s; break;
1381
            case 5: op = rv_op_fsub_d; break;
1382
            case 6: op = rv_op_fsub_h; break;
1383
            case 7: op = rv_op_fsub_q; break;
1384
            case 8: op = rv_op_fmul_s; break;
1385
            case 9: op = rv_op_fmul_d; break;
1386
            case 10: op = rv_op_fmul_h; break;
1387
            case 11: op = rv_op_fmul_q; break;
1388
            case 12: op = rv_op_fdiv_s; break;
1389
            case 13: op = rv_op_fdiv_d; break;
1390
            case 14: op = rv_op_fdiv_h; break;
1391
            case 15: op = rv_op_fdiv_q; break;
1392
            case 16:
1393
                switch (((inst >> 12) & 0b111)) {
1394
                case 0: op = rv_op_fsgnj_s; break;
1395
                case 1: op = rv_op_fsgnjn_s; break;
1396
                case 2: op = rv_op_fsgnjx_s; break;
1397
                }
1398
                break;
1399
            case 17:
1400
                switch (((inst >> 12) & 0b111)) {
1401
                case 0: op = rv_op_fsgnj_d; break;
1402
                case 1: op = rv_op_fsgnjn_d; break;
1403
                case 2: op = rv_op_fsgnjx_d; break;
1404
                }
1405
                break;
1406
            case 18:
1407
                switch (((inst >> 12) & 0b111)) {
1408
                case 0: op = rv_op_fsgnj_h; break;
1409
                case 1: op = rv_op_fsgnjn_h; break;
1410
                case 2: op = rv_op_fsgnjx_h; break;
1411
                }
1412
                break;
1413
            case 19:
1414
                switch (((inst >> 12) & 0b111)) {
1415
                case 0: op = rv_op_fsgnj_q; break;
1416
                case 1: op = rv_op_fsgnjn_q; break;
1417
                case 2: op = rv_op_fsgnjx_q; break;
1418
                }
1419
                break;
1420
            case 20:
1421
                switch (((inst >> 12) & 0b111)) {
1422
                case 0: op = rv_op_fmin_s; break;
1423
                case 1: op = rv_op_fmax_s; break;
1424
                }
1425
                break;
1426
            case 21:
1427
                switch (((inst >> 12) & 0b111)) {
1428
                case 0: op = rv_op_fmin_d; break;
1429
                case 1: op = rv_op_fmax_d; break;
1430
                }
1431
                break;
1432
            case 22:
1433
                switch (((inst >> 12) & 0b111)) {
1434
                case 0: op = rv_op_fmin_h; break;
1435
                case 1: op = rv_op_fmax_h; break;
1436
                }
1437
                break;
1438
            case 23:
1439
                switch (((inst >> 12) & 0b111)) {
1440
                case 0: op = rv_op_fmin_q; break;
1441
                case 1: op = rv_op_fmax_q; break;
1442
                }
1443
                break;
1444
            case 32:
1445
                switch (((inst >> 20) & 0b11111)) {
1446
                case 1: op = rv_op_fcvt_s_d; break;
1447
                case 2: op = rv_op_fcvt_s_h; break;
1448
                case 3: op = rv_op_fcvt_s_q; break;
1449
                }
1450
                break;
1451
            case 33:
1452
                switch (((inst >> 20) & 0b11111)) {
1453
                case 0: op = rv_op_fcvt_d_s; break;
1454
                case 2: op = rv_op_fcvt_d_h; break;
1455
                case 3: op = rv_op_fcvt_d_q; break;
1456
                }
1457
                break;
1458
            case 34:
1459
                switch (((inst >> 20) & 0b11111)) {
1460
                case 0: op = rv_op_fcvt_h_s; break;
1461
                case 1: op = rv_op_fcvt_h_d; break;
1462
                case 3: op = rv_op_fcvt_h_q; break;
1463
                }
1464
                break;
1465
            case 35:
1466
                switch (((inst >> 20) & 0b11111)) {
1467
                case 0: op = rv_op_fcvt_q_s; break;
1468
                case 1: op = rv_op_fcvt_q_d; break;
1469
                case 2: op = rv_op_fcvt_q_h; break;
1470
                }
1471
                break;
1472
            case 44:
1473
                switch (((inst >> 20) & 0b11111)) {
1474
                case 0: op = rv_op_fsqrt_s; break;
1475
                }
1476
                break;
1477
            case 45:
1478
                switch (((inst >> 20) & 0b11111)) {
1479
                case 0: op = rv_op_fsqrt_d; break;
1480
                }
1481
                break;
1482
            case 46:
1483
                switch (((inst >> 20) & 0b11111)) {
1484
                case 0: op = rv_op_fsqrt_h; break;
1485
                }
1486
                break;
1487
            case 47:
1488
                switch (((inst >> 20) & 0b11111)) {
1489
                case 0: op = rv_op_fsqrt_q; break;
1490
                }
1491
                break;
1492
            case 80:
1493
                switch (((inst >> 12) & 0b111)) {
1494
                case 0: op = rv_op_fle_s; break;
1495
                case 1: op = rv_op_flt_s; break;
1496
                case 2: op = rv_op_feq_s; break;
1497
                }
1498
                break;
1499
            case 81:
1500
                switch (((inst >> 12) & 0b111)) {
1501
                case 0: op = rv_op_fle_d; break;
1502
                case 1: op = rv_op_flt_d; break;
1503
                case 2: op = rv_op_feq_d; break;
1504
                }
1505
                break;
1506
            case 82:
1507
                switch (((inst >> 12) & 0b111)) {
1508
                case 0: op = rv_op_fle_h; break;
1509
                case 1: op = rv_op_flt_h; break;
1510
                case 2: op = rv_op_feq_h; break;
1511
                }
1512
                break;
1513
            case 83:
1514
                switch (((inst >> 12) & 0b111)) {
1515
                case 0: op = rv_op_fle_q; break;
1516
                case 1: op = rv_op_flt_q; break;
1517
                case 2: op = rv_op_feq_q; break;
1518
                }
1519
                break;
1520
            case 96:
1521
                switch (((inst >> 20) & 0b11111)) {
1522
                case 0: op = rv_op_fcvt_w_s; break;
1523
                case 1: op = rv_op_fcvt_wu_s; break;
1524
                case 2: op = rv_op_fcvt_l_s; break;
1525
                case 3: op = rv_op_fcvt_lu_s; break;
1526
                }
1527
                break;
1528
            case 97:
1529
                switch (((inst >> 20) & 0b11111)) {
1530
                case 0: op = rv_op_fcvt_w_d; break;
1531
                case 1: op = rv_op_fcvt_wu_d; break;
1532
                case 2: op = rv_op_fcvt_l_d; break;
1533
                case 3: op = rv_op_fcvt_lu_d; break;
1534
                }
1535
                break;
1536
            case 98:
1537
                switch (((inst >> 20) & 0b11111)) {
1538
                case 0: op = rv_op_fcvt_w_h; break;
1539
                case 1: op = rv_op_fcvt_wu_h; break;
1540
                case 2: op = rv_op_fcvt_l_h; break;
1541
                case 3: op = rv_op_fcvt_lu_h; break;
1542
                }
1543
                break;
1544
            case 99:
1545
                switch (((inst >> 20) & 0b11111)) {
1546
                case 0: op = rv_op_fcvt_w_q; break;
1547
                case 1: op = rv_op_fcvt_wu_q; break;
1548
                case 2: op = rv_op_fcvt_l_q; break;
1549
                case 3: op = rv_op_fcvt_lu_q; break;
1550
                }
1551
                break;
1552
            case 104:
1553
                switch (((inst >> 20) & 0b11111)) {
1554
                case 0: op = rv_op_fcvt_s_w; break;
1555
                case 1: op = rv_op_fcvt_s_wu; break;
1556
                case 2: op = rv_op_fcvt_s_l; break;
1557
                case 3: op = rv_op_fcvt_s_lu; break;
1558
                }
1559
                break;
1560
            case 105:
1561
                switch (((inst >> 20) & 0b11111)) {
1562
                case 0: op = rv_op_fcvt_d_w; break;
1563
                case 1: op = rv_op_fcvt_d_wu; break;
1564
                case 2: op = rv_op_fcvt_d_l; break;
1565
                case 3: op = rv_op_fcvt_d_lu; break;
1566
                }
1567
                break;
1568
            case 106:
1569
                switch (((inst >> 20) & 0b11111)) {
1570
                case 0: op = rv_op_fcvt_h_w; break;
1571
                case 1: op = rv_op_fcvt_h_wu; break;
1572
                case 2: op = rv_op_fcvt_h_l; break;
1573
                case 3: op = rv_op_fcvt_h_lu; break;
1574
                }
1575
                break;
1576
            case 107:
1577
                switch (((inst >> 20) & 0b11111)) {
1578
                case 0: op = rv_op_fcvt_q_w; break;
1579
                case 1: op = rv_op_fcvt_q_wu; break;
1580
                case 2: op = rv_op_fcvt_q_l; break;
1581
                case 3: op = rv_op_fcvt_q_lu; break;
1582
                }
1583
                break;
1584
            case 112:
1585
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1586
                case 0: op = rv_op_fmv_x_s; break;
1587
                case 1: op = rv_op_fclass_s; break;
1588
                }
1589
                break;
1590
            case 113:
1591
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1592
                case 0: op = rv_op_fmv_x_d; break;
1593
                case 1: op = rv_op_fclass_d; break;
1594
                }
1595
                break;
1596
            case 114:
1597
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1598
                case 0: op = rv_op_fmv_x_h; break;
1599
                case 1: op = rv_op_fclass_h; break;
1600
                }
1601
                break;
1602
            case 115:
1603
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1604
                case 0: op = rv_op_fmv_x_q; break;
1605
                case 1: op = rv_op_fclass_q; break;
1606
                }
1607
                break;
1608
            case 120:
1609
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1610
                case 0: op = rv_op_fmv_s_x; break;
1611
                }
1612
                break;
1613
            case 121:
1614
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1615
                case 0: op = rv_op_fmv_d_x; break;
1616
                }
1617
                break;
1618
            case 122:
1619
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1620
                case 0: op = rv_op_fmv_h_x; break;
1621
                }
1622
                break;
1623
            case 123:
1624
                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
1625
                case 0: op = rv_op_fmv_q_x; break;
1626
                }
1627
                break;
1628
            }
1629
            break;
1630
        case 22:
1631
            switch (((inst >> 12) & 0b111)) {
1632
            case 0: op = rv_op_addid; break;
1633
            case 1:
1634
                switch (((inst >> 26) & 0b111111)) {
1635
                case 0: op = rv_op_sllid; break;
1636
                }
1637
                break;
1638
            case 5:
1639
                switch (((inst >> 26) & 0b111111)) {
1640
                case 0: op = rv_op_srlid; break;
1641
                case 16: op = rv_op_sraid; break;
1642
                }
1643
                break;
1644
            }
1645
            break;
1646
        case 24:
1647
            switch (((inst >> 12) & 0b111)) {
1648
            case 0: op = rv_op_beq; break;
1649
            case 1: op = rv_op_bne; break;
1650
            case 4: op = rv_op_blt; break;
1651
            case 5: op = rv_op_bge; break;
1652
            case 6: op = rv_op_bltu; break;
1653
            case 7: op = rv_op_bgeu; break;
1654
            }
1655
            break;
1656
        case 25:
1657
            switch (((inst >> 12) & 0b111)) {
1658
            case 0: op = rv_op_jalr; break;
1659
            }
1660
            break;
1661
        case 27: op = rv_op_jal; break;
1662
        case 28:
1663
            switch (((inst >> 12) & 0b111)) {
1664
            case 0:
1665
                switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
1666
                case 0:
1667
                    switch (((inst >> 15) & 0b1111111111)) {
1668
                    case 0: op = rv_op_ecall; break;
1669
                    case 32: op = rv_op_ebreak; break;
1670
                    case 64: op = rv_op_uret; break;
1671
                    }
1672
                    break;
1673
                case 256:
1674
                    switch (((inst >> 20) & 0b11111)) {
1675
                    case 2:
1676
                        switch (((inst >> 15) & 0b11111)) {
1677
                        case 0: op = rv_op_sret; break;
1678
                        }
1679
                        break;
1680
                    case 4: op = rv_op_sfence_vm; break;
1681
                    case 5:
1682
                        switch (((inst >> 15) & 0b11111)) {
1683
                        case 0: op = rv_op_wfi; break;
1684
                        }
1685
                        break;
1686
                    }
1687
                    break;
1688
                case 288: op = rv_op_sfence_vma; break;
1689
                case 512:
1690
                    switch (((inst >> 15) & 0b1111111111)) {
1691
                    case 64: op = rv_op_hret; break;
1692
                    }
1693
                    break;
1694
                case 768:
1695
                    switch (((inst >> 15) & 0b1111111111)) {
1696
                    case 64: op = rv_op_mret; break;
1697
                    }
1698
                    break;
1699
                case 1952:
1700
                    switch (((inst >> 15) & 0b1111111111)) {
1701
                    case 576: op = rv_op_dret; break;
1702
                    }
1703
                    break;
1704
                }
1705
                break;
1706
            case 1: op = rv_op_csrrw; break;
1707
            case 2: op = rv_op_csrrs; break;
1708
            case 3: op = rv_op_csrrc; break;
1709
            case 5: op = rv_op_csrrwi; break;
1710
            case 6: op = rv_op_csrrsi; break;
1711
            case 7: op = rv_op_csrrci; break;
1712
            }
1713
            break;
1714
        case 30:
1715
            switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
1716
            case 0: op = rv_op_addd; break;
1717
            case 1: op = rv_op_slld; break;
1718
            case 5: op = rv_op_srld; break;
1719
            case 8: op = rv_op_muld; break;
1720
            case 12: op = rv_op_divd; break;
1721
            case 13: op = rv_op_divud; break;
1722
            case 14: op = rv_op_remd; break;
1723
            case 15: op = rv_op_remud; break;
1724
            case 256: op = rv_op_subd; break;
1725
            case 261: op = rv_op_srad; break;
1726
            }
1727
            break;
1728
        }
1729
        break;
1730
    }
1731
    dec->op = op;
1732
}
1733

1734
/* operand extractors */
1735

1736
static uint32_t operand_rd(rv_inst inst) {
1737
    return (inst << 52) >> 59;
1738
}
1739

1740
static uint32_t operand_rs1(rv_inst inst) {
1741
    return (inst << 44) >> 59;
1742
}
1743

1744
static uint32_t operand_rs2(rv_inst inst) {
1745
    return (inst << 39) >> 59;
1746
}
1747

1748
static uint32_t operand_rs3(rv_inst inst) {
1749
    return (inst << 32) >> 59;
1750
}
1751

1752
static uint32_t operand_aq(rv_inst inst) {
1753
    return (inst << 37) >> 63;
1754
}
1755

1756
static uint32_t operand_rl(rv_inst inst) {
1757
    return (inst << 38) >> 63;
1758
}
1759

1760
static uint32_t operand_pred(rv_inst inst) {
1761
    return (inst << 36) >> 60;
1762
}
1763

1764
static uint32_t operand_succ(rv_inst inst) {
1765
    return (inst << 40) >> 60;
1766
}
1767

1768
static uint32_t operand_rm(rv_inst inst) {
1769
    return (inst << 49) >> 61;
1770
}
1771

1772
static uint32_t operand_shamt5(rv_inst inst) {
1773
    return (inst << 39) >> 59;
1774
}
1775

1776
static uint32_t operand_shamt6(rv_inst inst) {
1777
    return (inst << 38) >> 58;
1778
}
1779

1780
static uint32_t operand_shamt7(rv_inst inst) {
1781
    return (inst << 37) >> 57;
1782
}
1783

1784
static uint32_t operand_crdq(rv_inst inst) {
1785
    return (inst << 59) >> 61;
1786
}
1787

1788
static uint32_t operand_crs1q(rv_inst inst) {
1789
    return (inst << 54) >> 61;
1790
}
1791

1792
static uint32_t operand_crs1rdq(rv_inst inst) {
1793
    return (inst << 54) >> 61;
1794
}
1795

1796
static uint32_t operand_crs2q(rv_inst inst) {
1797
    return (inst << 59) >> 61;
1798
}
1799

1800
static uint32_t operand_crd(rv_inst inst) {
1801
    return (inst << 52) >> 59;
1802
}
1803

1804
static uint32_t operand_crs1(rv_inst inst) {
1805
    return (inst << 52) >> 59;
1806
}
1807

1808
static uint32_t operand_crs1rd(rv_inst inst) {
1809
    return (inst << 52) >> 59;
1810
}
1811

1812
static uint32_t operand_crs2(rv_inst inst) {
1813
    return (inst << 57) >> 59;
1814
}
1815

1816
static uint32_t operand_cimmsh5(rv_inst inst) {
1817
    return (inst << 57) >> 59;
1818
}
1819

1820
static uint32_t operand_csr12(rv_inst inst) {
1821
    return (inst << 32) >> 52;
1822
}
1823

1824
static int32_t operand_imm12(rv_inst inst) {
1825
    return ((int64_t)inst << 32) >> 52;
1826
}
1827

1828
static int32_t operand_imm20(rv_inst inst) {
1829
    return (((int64_t)inst << 32) >> 44) << 12;
1830
}
1831

1832
static int32_t operand_jimm20(rv_inst inst) {
1833
    return (((int64_t)inst << 32) >> 63) << 20 |
1834
        ((inst << 33) >> 54) << 1 |
1835
        ((inst << 43) >> 63) << 11 |
1836
        ((inst << 44) >> 56) << 12;
1837
}
1838

1839
static int32_t operand_simm12(rv_inst inst) {
1840
    return (((int64_t)inst << 32) >> 57) << 5 |
1841
        (inst << 52) >> 59;
1842
}
1843

1844
static int32_t operand_sbimm12(rv_inst inst) {
1845
    return (((int64_t)inst << 32) >> 63) << 12 |
1846
        ((inst << 33) >> 58) << 5 |
1847
        ((inst << 52) >> 60) << 1 |
1848
        ((inst << 56) >> 63) << 11;
1849
}
1850

1851
static uint32_t operand_cimmsh6(rv_inst inst) {
1852
    return ((inst << 51) >> 63) << 5 |
1853
        (inst << 57) >> 59;
1854
}
1855

1856
static int32_t operand_cimmi(rv_inst inst) {
1857
    return (((int64_t)inst << 51) >> 63) << 5 |
1858
        (inst << 57) >> 59;
1859
}
1860

1861
static int32_t operand_cimmui(rv_inst inst) {
1862
    return (((int64_t)inst << 51) >> 63) << 17 |
1863
        ((inst << 57) >> 59) << 12;
1864
}
1865

1866
static uint32_t operand_cimmlwsp(rv_inst inst) {
1867
    return ((inst << 51) >> 63) << 5 |
1868
        ((inst << 57) >> 61) << 2 |
1869
        ((inst << 60) >> 62) << 6;
1870
}
1871

1872
static uint32_t operand_cimmldsp(rv_inst inst) {
1873
    return ((inst << 51) >> 63) << 5 |
1874
        ((inst << 57) >> 62) << 3 |
1875
        ((inst << 59) >> 61) << 6;
1876
}
1877

1878
static uint32_t operand_cimmlqsp(rv_inst inst) {
1879
    return ((inst << 51) >> 63) << 5 |
1880
        ((inst << 57) >> 63) << 4 |
1881
        ((inst << 58) >> 60) << 6;
1882
}
1883

1884
static int32_t operand_cimm16sp(rv_inst inst) {
1885
    return (((int64_t)inst << 51) >> 63) << 9 |
1886
        ((inst << 57) >> 63) << 4 |
1887
        ((inst << 58) >> 63) << 6 |
1888
        ((inst << 59) >> 62) << 7 |
1889
        ((inst << 61) >> 63) << 5;
1890
}
1891

1892
static int32_t operand_cimmj(rv_inst inst) {
1893
    return (((int64_t)inst << 51) >> 63) << 11 |
1894
        ((inst << 52) >> 63) << 4 |
1895
        ((inst << 53) >> 62) << 8 |
1896
        ((inst << 55) >> 63) << 10 |
1897
        ((inst << 56) >> 63) << 6 |
1898
        ((inst << 57) >> 63) << 7 |
1899
        ((inst << 58) >> 61) << 1 |
1900
        ((inst << 61) >> 63) << 5;
1901
}
1902

1903
static int32_t operand_cimmb(rv_inst inst) {
1904
    return (((int64_t)inst << 51) >> 63) << 8 |
1905
        ((inst << 52) >> 62) << 3 |
1906
        ((inst << 57) >> 62) << 6 |
1907
        ((inst << 59) >> 62) << 1 |
1908
        ((inst << 61) >> 63) << 5;
1909
}
1910

1911
static uint32_t operand_cimmswsp(rv_inst inst) {
1912
    return ((inst << 51) >> 60) << 2 |
1913
        ((inst << 55) >> 62) << 6;
1914
}
1915

1916
static uint32_t operand_cimmsdsp(rv_inst inst) {
1917
    return ((inst << 51) >> 61) << 3 |
1918
        ((inst << 54) >> 61) << 6;
1919
}
1920

1921
static uint32_t operand_cimmsqsp(rv_inst inst) {
1922
    return ((inst << 51) >> 62) << 4 |
1923
        ((inst << 53) >> 60) << 6;
1924
}
1925

1926
static uint32_t operand_cimm4spn(rv_inst inst) {
1927
    return ((inst << 51) >> 62) << 4 |
1928
        ((inst << 53) >> 60) << 6 |
1929
        ((inst << 57) >> 63) << 2 |
1930
        ((inst << 58) >> 63) << 3;
1931
}
1932

1933
static uint32_t operand_cimmw(rv_inst inst) {
1934
    return ((inst << 51) >> 61) << 3 |
1935
        ((inst << 57) >> 63) << 2 |
1936
        ((inst << 58) >> 63) << 6;
1937
}
1938

1939
static uint32_t operand_cimmd(rv_inst inst) {
1940
    return ((inst << 51) >> 61) << 3 |
1941
        ((inst << 57) >> 62) << 6;
1942
}
1943

1944
static uint32_t operand_cimmq(rv_inst inst) {
1945
    return ((inst << 51) >> 62) << 4 |
1946
        ((inst << 53) >> 63) << 8 |
1947
        ((inst << 57) >> 62) << 6;
1948
}
1949

1950
/* decode operands */
1951

1952
static void decode_inst_operands(rv_decode *dec)
1953
{
1954
    rv_inst inst = dec->inst;
1955
    dec->codec = opcode_data[dec->op].codec;
1956
    switch (dec->codec) {
1957
    case rv_codec_none:
1958
        dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
1959
        dec->imm = 0;
1960
        break;
1961
    case rv_codec_u:
1962
        dec->rd = operand_rd(inst);
1963
        dec->rs1 = dec->rs2 = rv_ireg_zero;
1964
        dec->imm = operand_imm20(inst);
1965
        break;
1966
    case rv_codec_uj:
1967
        dec->rd = operand_rd(inst);
1968
        dec->rs1 = dec->rs2 = rv_ireg_zero;
1969
        dec->imm = operand_jimm20(inst);
1970
        break;
1971
    case rv_codec_i:
1972
        dec->rd = operand_rd(inst);
1973
        dec->rs1 = operand_rs1(inst);
1974
        dec->rs2 = rv_ireg_zero;
1975
        dec->imm = operand_imm12(inst);
1976
        break;
1977
    case rv_codec_i_sh5:
1978
        dec->rd = operand_rd(inst);
1979
        dec->rs1 = operand_rs1(inst);
1980
        dec->rs2 = rv_ireg_zero;
1981
        dec->imm = operand_shamt5(inst);
1982
        break;
1983
    case rv_codec_i_sh6:
1984
        dec->rd = operand_rd(inst);
1985
        dec->rs1 = operand_rs1(inst);
1986
        dec->rs2 = rv_ireg_zero;
1987
        dec->imm = operand_shamt6(inst);
1988
        break;
1989
    case rv_codec_i_sh7:
1990
        dec->rd = operand_rd(inst);
1991
        dec->rs1 = operand_rs1(inst);
1992
        dec->rs2 = rv_ireg_zero;
1993
        dec->imm = operand_shamt7(inst);
1994
        break;
1995
    case rv_codec_i_csr:
1996
        dec->rd = operand_rd(inst);
1997
        dec->rs1 = operand_rs1(inst);
1998
        dec->rs2 = rv_ireg_zero;
1999
        dec->imm = operand_csr12(inst);
2000
        break;
2001
    case rv_codec_s:
2002
        dec->rd = rv_ireg_zero;
2003
        dec->rs1 = operand_rs1(inst);
2004
        dec->rs2 = operand_rs2(inst);
2005
        dec->imm = operand_simm12(inst);
2006
        break;
2007
    case rv_codec_sb:
2008
        dec->rd = rv_ireg_zero;
2009
        dec->rs1 = operand_rs1(inst);
2010
        dec->rs2 = operand_rs2(inst);
2011
        dec->imm = operand_sbimm12(inst);
2012
        break;
2013
    case rv_codec_r:
2014
        dec->rd = operand_rd(inst);
2015
        dec->rs1 = operand_rs1(inst);
2016
        dec->rs2 = operand_rs2(inst);
2017
        dec->imm = 0;
2018
        break;
2019
    case rv_codec_r_m:
2020
        dec->rd = operand_rd(inst);
2021
        dec->rs1 = operand_rs1(inst);
2022
        dec->rs2 = operand_rs2(inst);
2023
        dec->imm = 0;
2024
        dec->rm = operand_rm(inst);
2025
        break;
2026
    case rv_codec_r4_m:
2027
        dec->rd = operand_rd(inst);
2028
        dec->rs1 = operand_rs1(inst);
2029
        dec->rs2 = operand_rs2(inst);
2030
        dec->rs3 = operand_rs3(inst);
2031
        dec->imm = 0;
2032
        dec->rm = operand_rm(inst);
2033
        break;
2034
    case rv_codec_r_a:
2035
        dec->rd = operand_rd(inst);
2036
        dec->rs1 = operand_rs1(inst);
2037
        dec->rs2 = operand_rs2(inst);
2038
        dec->imm = 0;
2039
        dec->aq = operand_aq(inst);
2040
        dec->rl = operand_rl(inst);
2041
        break;
2042
    case rv_codec_r_l:
2043
        dec->rd = operand_rd(inst);
2044
        dec->rs1 = operand_rs1(inst);
2045
        dec->rs2 = rv_ireg_zero;
2046
        dec->imm = 0;
2047
        dec->aq = operand_aq(inst);
2048
        dec->rl = operand_rl(inst);
2049
        break;
2050
    case rv_codec_r_f:
2051
        dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
2052
        dec->pred = operand_pred(inst);
2053
        dec->succ = operand_succ(inst);
2054
        dec->imm = 0;
2055
        break;
2056
    case rv_codec_cb:
2057
        dec->rd = rv_ireg_zero;
2058
        dec->rs1 = operand_crs1q(inst) + 8;
2059
        dec->rs2 = rv_ireg_zero;
2060
        dec->imm = operand_cimmb(inst);
2061
        break;
2062
    case rv_codec_cb_imm:
2063
        dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
2064
        dec->rs2 = rv_ireg_zero;
2065
        dec->imm = operand_cimmi(inst);
2066
        break;
2067
    case rv_codec_cb_sh5:
2068
        dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
2069
        dec->rs2 = rv_ireg_zero;
2070
        dec->imm = operand_cimmsh5(inst);
2071
        break;
2072
    case rv_codec_cb_sh6:
2073
        dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
2074
        dec->rs2 = rv_ireg_zero;
2075
        dec->imm = operand_cimmsh6(inst);
2076
        break;
2077
    case rv_codec_ci:
2078
        dec->rd = dec->rs1 = operand_crs1rd(inst);
2079
        dec->rs2 = rv_ireg_zero;
2080
        dec->imm = operand_cimmi(inst);
2081
        break;
2082
    case rv_codec_ci_sh5:
2083
        dec->rd = dec->rs1 = operand_crs1rd(inst);
2084
        dec->rs2 = rv_ireg_zero;
2085
        dec->imm = operand_cimmsh5(inst);
2086
        break;
2087
    case rv_codec_ci_sh6:
2088
        dec->rd = dec->rs1 = operand_crs1rd(inst);
2089
        dec->rs2 = rv_ireg_zero;
2090
        dec->imm = operand_cimmsh6(inst);
2091
        break;
2092
    case rv_codec_ci_16sp:
2093
        dec->rd = rv_ireg_sp;
2094
        dec->rs1 = rv_ireg_sp;
2095
        dec->rs2 = rv_ireg_zero;
2096
        dec->imm = operand_cimm16sp(inst);
2097
        break;
2098
    case rv_codec_ci_lwsp:
2099
        dec->rd = operand_crd(inst);
2100
        dec->rs1 = rv_ireg_sp;
2101
        dec->rs2 = rv_ireg_zero;
2102
        dec->imm = operand_cimmlwsp(inst);
2103
        break;
2104
    case rv_codec_ci_ldsp:
2105
        dec->rd = operand_crd(inst);
2106
        dec->rs1 = rv_ireg_sp;
2107
        dec->rs2 = rv_ireg_zero;
2108
        dec->imm = operand_cimmldsp(inst);
2109
        break;
2110
    case rv_codec_ci_lqsp:
2111
        dec->rd = operand_crd(inst);
2112
        dec->rs1 = rv_ireg_sp;
2113
        dec->rs2 = rv_ireg_zero;
2114
        dec->imm = operand_cimmlqsp(inst);
2115
        break;
2116
    case rv_codec_ci_li:
2117
        dec->rd = operand_crd(inst);
2118
        dec->rs1 = rv_ireg_zero;
2119
        dec->rs2 = rv_ireg_zero;
2120
        dec->imm = operand_cimmi(inst);
2121
        break;
2122
    case rv_codec_ci_lui:
2123
        dec->rd = operand_crd(inst);
2124
        dec->rs1 = rv_ireg_zero;
2125
        dec->rs2 = rv_ireg_zero;
2126
        dec->imm = operand_cimmui(inst);
2127
        break;
2128
    case rv_codec_ci_none:
2129
        dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
2130
        dec->imm = 0;
2131
        break;
2132
    case rv_codec_ciw_4spn:
2133
        dec->rd = operand_crdq(inst) + 8;
2134
        dec->rs1 = rv_ireg_sp;
2135
        dec->rs2 = rv_ireg_zero;
2136
        dec->imm = operand_cimm4spn(inst);
2137
        break;
2138
    case rv_codec_cj:
2139
        dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
2140
        dec->imm = operand_cimmj(inst);
2141
        break;
2142
    case rv_codec_cj_jal:
2143
        dec->rd = rv_ireg_ra;
2144
        dec->rs1 = dec->rs2 = rv_ireg_zero;
2145
        dec->imm = operand_cimmj(inst);
2146
        break;
2147
    case rv_codec_cl_lw:
2148
        dec->rd = operand_crdq(inst) + 8;
2149
        dec->rs1 = operand_crs1q(inst) + 8;
2150
        dec->rs2 = rv_ireg_zero;
2151
        dec->imm = operand_cimmw(inst);
2152
        break;
2153
    case rv_codec_cl_ld:
2154
        dec->rd = operand_crdq(inst) + 8;
2155
        dec->rs1 = operand_crs1q(inst) + 8;
2156
        dec->rs2 = rv_ireg_zero;
2157
        dec->imm = operand_cimmd(inst);
2158
        break;
2159
    case rv_codec_cl_lq:
2160
        dec->rd = operand_crdq(inst) + 8;
2161
        dec->rs1 = operand_crs1q(inst) + 8;
2162
        dec->rs2 = rv_ireg_zero;
2163
        dec->imm = operand_cimmq(inst);
2164
        break;
2165
    case rv_codec_cr:
2166
        dec->rd = dec->rs1 = operand_crs1rd(inst);
2167
        dec->rs2 = operand_crs2(inst);
2168
        dec->imm = 0;
2169
        break;
2170
    case rv_codec_cr_mv:
2171
        dec->rd = operand_crd(inst);
2172
        dec->rs1 = operand_crs2(inst);
2173
        dec->rs2 = rv_ireg_zero;
2174
        dec->imm = 0;
2175
        break;
2176
    case rv_codec_cr_jalr:
2177
        dec->rd = rv_ireg_ra;
2178
        dec->rs1 = operand_crs1(inst);
2179
        dec->rs2 = rv_ireg_zero;
2180
        dec->imm = 0;
2181
        break;
2182
    case rv_codec_cr_jr:
2183
        dec->rd = rv_ireg_zero;
2184
        dec->rs1 = operand_crs1(inst);
2185
        dec->rs2 = rv_ireg_zero;
2186
        dec->imm = 0;
2187
        break;
2188
    case rv_codec_cs:
2189
        dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
2190
        dec->rs2 = operand_crs2q(inst) + 8;
2191
        dec->imm = 0;
2192
        break;
2193
    case rv_codec_cs_sw:
2194
        dec->rd = rv_ireg_zero;
2195
        dec->rs1 = operand_crs1q(inst) + 8;
2196
        dec->rs2 = operand_crs2q(inst) + 8;
2197
        dec->imm = operand_cimmw(inst);
2198
        break;
2199
    case rv_codec_cs_sd:
2200
        dec->rd = rv_ireg_zero;
2201
        dec->rs1 = operand_crs1q(inst) + 8;
2202
        dec->rs2 = operand_crs2q(inst) + 8;
2203
        dec->imm = operand_cimmd(inst);
2204
        break;
2205
    case rv_codec_cs_sq:
2206
        dec->rd = rv_ireg_zero;
2207
        dec->rs1 = operand_crs1q(inst) + 8;
2208
        dec->rs2 = operand_crs2q(inst) + 8;
2209
        dec->imm = operand_cimmq(inst);
2210
        break;
2211
    case rv_codec_css_swsp:
2212
        dec->rd = rv_ireg_zero;
2213
        dec->rs1 = rv_ireg_sp;
2214
        dec->rs2 = operand_crs2(inst);
2215
        dec->imm = operand_cimmswsp(inst);
2216
        break;
2217
    case rv_codec_css_sdsp:
2218
        dec->rd = rv_ireg_zero;
2219
        dec->rs1 = rv_ireg_sp;
2220
        dec->rs2 = operand_crs2(inst);
2221
        dec->imm = operand_cimmsdsp(inst);
2222
        break;
2223
    case rv_codec_css_sqsp:
2224
        dec->rd = rv_ireg_zero;
2225
        dec->rs1 = rv_ireg_sp;
2226
        dec->rs2 = operand_crs2(inst);
2227
        dec->imm = operand_cimmsqsp(inst);
2228
        break;
2229
    };
2230
}
2231

2232
/* decompress instruction */
2233

2234
static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
2235
{
2236
    int decomp_op;
2237
    switch (isa) {
2238
    case rv32: decomp_op = opcode_data[dec->op].decomp_rv32; break;
2239
    case rv64: decomp_op = opcode_data[dec->op].decomp_rv64; break;
2240
    case rv128: decomp_op = opcode_data[dec->op].decomp_rv128; break;
2241
    }
2242
    if (decomp_op != rv_op_illegal) {
2243
        if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) && dec->imm == 0) {
2244
            dec->op = rv_op_illegal;
2245
        } else {
2246
            dec->op = decomp_op;
2247
            dec->codec = opcode_data[decomp_op].codec;
2248
        }
2249
    }
2250
}
2251

2252
/* check constraint */
2253

2254
static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
2255
{
2256
    if (c == rvcc_last)
2257
        return false;
2258

2259
    int32_t imm = dec->imm;
2260
    uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
2261
    while (*c != rvc_end) {
2262
        switch (*c) {
2263
        case rvc_rd_eq_ra: if (!(rd == 1)) return false; break;
2264
        case rvc_rd_eq_x0: if (!(rd == 0)) return false; break;
2265
        case rvc_rs1_eq_x0: if (!(rs1 == 0)) return false; break;
2266
        case rvc_rs2_eq_x0: if (!(rs2 == 0)) return false; break;
2267
        case rvc_rs2_eq_rs1: if (!(rs2 == rs1)) return false; break;
2268
        case rvc_rs1_eq_ra: if (!(rs1 == 1)) return false; break;
2269
        case rvc_imm_eq_zero: if (!(imm == 0)) return false; break;
2270
        case rvc_imm_eq_n1: if (!(imm == -1)) return false; break;
2271
        case rvc_imm_eq_p1: if (!(imm == 1)) return false; break;
2272
        case rvc_csr_eq_0x001: if (!(imm == 0x001)) return false; break;
2273
        case rvc_csr_eq_0x002: if (!(imm == 0x002)) return false; break;
2274
        case rvc_csr_eq_0x003: if (!(imm == 0x003)) return false; break;
2275
        case rvc_csr_eq_0xc00: if (!(imm == 0xc00)) return false; break;
2276
        case rvc_csr_eq_0xc01: if (!(imm == 0xc01)) return false; break;
2277
        case rvc_csr_eq_0xc02: if (!(imm == 0xc02)) return false; break;
2278
        case rvc_csr_eq_0xc80: if (!(imm == 0xc80)) return false; break;
2279
        case rvc_csr_eq_0xc81: if (!(imm == 0xc81)) return false; break;
2280
        case rvc_csr_eq_0xc82: if (!(imm == 0xc82)) return false; break;
2281
        default: break;
2282
        }
2283
        c++;
2284
    }
2285
    return true;
2286
}
2287

2288
/* lift instruction to pseudo-instruction */
2289

2290
static void decode_inst_lift_pseudo(rv_decode *dec)
2291
{
2292
    const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
2293
    if (!comp_data) {
2294
        return;
2295
    }
2296
    while (comp_data->constraints) {
2297
        if (check_constraints(dec, comp_data->constraints)) {
2298
            dec->op = comp_data->op;
2299
            dec->codec = opcode_data[dec->op].codec;
2300
            return;
2301
        }
2302
        comp_data++;
2303
    }
2304
}
2305

2306
/* format instruction */
2307

2308
static char *append(char *buf, const char *src, const char *end)
2309
{
2310
    while (buf < end && *src)
2311
        *buf++ = *src++;
2312
    return buf;
2313
}
2314

2315
#define INST_FMT_2 "%04" PRIx64 "              "
2316
#define INST_FMT_4 "%08" PRIx64 "          "
2317
#define INST_FMT_6 "%012" PRIx64 "      "
2318
#define INST_FMT_8 "%016" PRIx64 "  "
2319

2320
static void decode_inst_format(char *buf, size_t buflen, size_t tab, rv_decode *dec)
2321
{
2322
    char tmp[64];
2323
    const char *fmt;
2324
    const char *start = buf;
2325
    const char *end = &buf[buflen];
2326

2327
    size_t len = riscv_inst_length(dec->inst);
2328
    switch (len) {
2329
    case 2:
2330
        buf += snprintf(buf, buflen, INST_FMT_2, dec->inst);
2331
        break;
2332
    case 4:
2333
        buf += snprintf(buf, buflen, INST_FMT_4, dec->inst);
2334
        break;
2335
    case 6:
2336
        buf += snprintf(buf, buflen, INST_FMT_6, dec->inst);
2337
        break;
2338
    default:
2339
        buf += snprintf(buf, buflen, INST_FMT_8, dec->inst);
2340
        break;
2341
    }
2342

2343
    fmt = opcode_data[dec->op].format;
2344
    while (*fmt) {
2345
        switch (*fmt) {
2346
        case 'O':
2347
            buf = append(buf, opcode_data[dec->op].name, end);
2348
            break;
2349
        case '(':
2350
            buf = append(buf, "(", end);
2351
            break;
2352
        case ',':
2353
            buf = append(buf, ",", end);
2354
            break;
2355
        case ')':
2356
            buf = append(buf, ")", end);
2357
            break;
2358
        case '0':
2359
            buf = append(buf, rv_ireg_name_sym[dec->rd], end);
2360
            break;
2361
        case '1':
2362
            buf = append(buf, rv_ireg_name_sym[dec->rs1], end);
2363
            break;
2364
        case '2':
2365
            buf = append(buf, rv_ireg_name_sym[dec->rs2], end);
2366
            break;
2367
        case '3':
2368
            buf = append(buf, rv_freg_name_sym[dec->rd], end);
2369
            break;
2370
        case '4':
2371
            buf = append(buf, rv_freg_name_sym[dec->rs1], end);
2372
            break;
2373
        case '5':
2374
            buf = append(buf, rv_freg_name_sym[dec->rs2], end);
2375
            break;
2376
        case '6':
2377
            buf = append(buf, rv_freg_name_sym[dec->rs3], end);
2378
            break;
2379
        case '7':
2380
            snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
2381
            buf = append(buf, tmp, end);
2382
            break;
2383
        case 'i':
2384
            snprintf(tmp, sizeof(tmp), "%d", dec->imm);
2385
            buf = append(buf, tmp, end);
2386
            break;
2387
        case 'o':
2388
            snprintf(tmp, sizeof(tmp), "%d", dec->imm);
2389
            buf = append(buf, tmp, end);
2390
            while (buf < &start[2*tab]) {
2391
                *buf++ = ' ';
2392
            }
2393
            snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
2394
                dec->pc + dec->imm);
2395
            buf = append(buf, tmp, end);
2396
            break;
2397
        case 'c': {
2398
            const char *name = csr_name(dec->imm & 0xfff);
2399
            if (name) {
2400
                buf = append(buf, name, end);
2401
            } else {
2402
                snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);
2403
                buf = append(buf, tmp, end);
2404
            }
2405
            break;
2406
        }
2407
        case 'r':
2408
            switch (dec->rm) {
2409
            case rv_rm_rne:
2410
                buf = append(buf, "rne", end);
2411
                break;
2412
            case rv_rm_rtz:
2413
                buf = append(buf, "rtz", end);
2414
                break;
2415
            case rv_rm_rdn:
2416
                buf = append(buf, "rdn", end);
2417
                break;
2418
            case rv_rm_rup:
2419
                buf = append(buf, "rup", end);
2420
                break;
2421
            case rv_rm_rmm:
2422
                buf = append(buf, "rmm", end);
2423
                break;
2424
            case rv_rm_dyn:
2425
                buf = append(buf, "dyn", end);
2426
                break;
2427
            default:
2428
                buf = append(buf, "inv", end);
2429
                break;
2430
            }
2431
            break;
2432
        case 'p':
2433
            if (dec->pred & rv_fence_i) {
2434
                buf = append(buf, "i", end);
2435
            }
2436
            if (dec->pred & rv_fence_o) {
2437
                buf = append(buf, "o", end);
2438
            }
2439
            if (dec->pred & rv_fence_r) {
2440
                buf = append(buf, "r", end);
2441
            }
2442
            if (dec->pred & rv_fence_w) {
2443
                buf = append(buf, "w", end);
2444
            }
2445
            break;
2446
        case 's':
2447
            if (dec->succ & rv_fence_i) {
2448
                buf = append(buf, "i", end);
2449
            }
2450
            if (dec->succ & rv_fence_o) {
2451
                buf = append(buf, "o", end);
2452
            }
2453
            if (dec->succ & rv_fence_r) {
2454
                buf = append(buf, "r", end);
2455
            }
2456
            if (dec->succ & rv_fence_w) {
2457
                buf = append(buf, "w", end);
2458
            }
2459
            break;
2460
        case '\t':
2461
            while (buf < &start[tab]) {
2462
                *buf++ = ' ';
2463
            }
2464
            break;
2465
        case 'A':
2466
            if (dec->aq) {
2467
                buf = append(buf, ".aq", end);
2468
            }
2469
            break;
2470
        case 'R':
2471
            if (dec->rl) {
2472
                buf = append(buf, ".rl", end);
2473
            }
2474
            break;
2475
        default:
2476
            break;
2477
        }
2478
        fmt++;
2479
    }
2480
    *buf = '\0';
2481
}
2482

2483
/* instruction length */
2484

2485
size_t riscv_inst_length(rv_inst inst)
2486
{
2487
    /* NOTE: supports maximum instruction size of 64-bits */
2488

2489
    /* instruction length coding
2490
     *
2491
     *      aa - 16 bit aa != 11
2492
     *   bbb11 - 32 bit bbb != 111
2493
     *  011111 - 48 bit
2494
     * 0111111 - 64 bit
2495
     */
2496

2497
    return (inst &      0b11) != 0b11      ? 2
2498
         : (inst &   0b11100) != 0b11100   ? 4
2499
         : (inst &  0b111111) == 0b011111  ? 6
2500
         : (inst & 0b1111111) == 0b0111111 ? 8
2501
         : 0;
2502
}
2503

2504
/* instruction fetch */
2505

2506
void riscv_inst_fetch(const uint8_t *data, rv_inst *instp, size_t *length)
2507
{
2508
    rv_inst inst = ((rv_inst)data[1] << 8) | ((rv_inst)data[0]);
2509
    size_t len = *length = riscv_inst_length(inst);
2510
    if (len >= 8) inst |= ((rv_inst)data[7] << 56) | ((rv_inst)data[6] << 48);
2511
    if (len >= 6) inst |= ((rv_inst)data[5] << 40) | ((rv_inst)data[4] << 32);
2512
    if (len >= 4) inst |= ((rv_inst)data[3] << 24) | ((rv_inst)data[2] << 16);
2513
    *instp = inst;
2514
}
2515

2516
/* disassemble instruction */
2517

2518
void riscv_disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
2519
{
2520
    rv_decode dec{};
2521
    dec.pc = pc;
2522
    dec.inst = inst;
2523
    decode_inst_opcode(&dec, isa);
2524
    decode_inst_operands(&dec);
2525
    decode_inst_decompress(&dec, isa);
2526
    decode_inst_lift_pseudo(&dec);
2527
    decode_inst_format(buf, buflen, 32, &dec);
2528
}
2529

2530
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