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Path: blob/master/ext/riscv-disas.h
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/*1* RISC-V Disassembler2*3* Copyright (c) 2016-2017 Michael Clark <[email protected]>4* Copyright (c) 2017-2018 SiFive, Inc.5*6* Permission is hereby granted, free of charge, to any person obtaining a copy7* of this software and associated documentation files (the "Software"), to deal8* in the Software without restriction, including without limitation the rights9* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell10* copies of the Software, and to permit persons to whom the Software is11* furnished to do so, subject to the following conditions:12*13* The above copyright notice and this permission notice shall be included in14* all copies or substantial portions of the Software.15*16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,21* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN22* THE SOFTWARE.23*/2425#ifndef RISCV_DISASSEMBLER_H26#define RISCV_DISASSEMBLER_H2728#include <cstdint>2930/* types */3132typedef uint64_t rv_inst;33typedef uint16_t rv_opcode;3435/* enums */3637typedef enum {38rv32,39rv64,40rv12841} rv_isa;4243typedef enum {44rv_rm_rne = 0,45rv_rm_rtz = 1,46rv_rm_rdn = 2,47rv_rm_rup = 3,48rv_rm_rmm = 4,49rv_rm_dyn = 7,50} rv_rm;5152typedef enum {53rv_fence_i = 8,54rv_fence_o = 4,55rv_fence_r = 2,56rv_fence_w = 1,57} rv_fence;5859typedef enum {60rv_ireg_zero,61rv_ireg_ra,62rv_ireg_sp,63rv_ireg_gp,64rv_ireg_tp,65rv_ireg_t0,66rv_ireg_t1,67rv_ireg_t2,68rv_ireg_s0,69rv_ireg_s1,70rv_ireg_a0,71rv_ireg_a1,72rv_ireg_a2,73rv_ireg_a3,74rv_ireg_a4,75rv_ireg_a5,76rv_ireg_a6,77rv_ireg_a7,78rv_ireg_s2,79rv_ireg_s3,80rv_ireg_s4,81rv_ireg_s5,82rv_ireg_s6,83rv_ireg_s7,84rv_ireg_s8,85rv_ireg_s9,86rv_ireg_s10,87rv_ireg_s11,88rv_ireg_t3,89rv_ireg_t4,90rv_ireg_t5,91rv_ireg_t6,92} rv_ireg;9394typedef enum {95rvc_end,96rvc_rd_eq_ra,97rvc_rd_eq_x0,98rvc_rs1_eq_x0,99rvc_rs2_eq_x0,100rvc_rs2_eq_rs1,101rvc_rs1_eq_ra,102rvc_imm_eq_zero,103rvc_imm_eq_n1,104rvc_imm_eq_p1,105rvc_csr_eq_0x001,106rvc_csr_eq_0x002,107rvc_csr_eq_0x003,108rvc_csr_eq_0xc00,109rvc_csr_eq_0xc01,110rvc_csr_eq_0xc02,111rvc_csr_eq_0xc80,112rvc_csr_eq_0xc81,113rvc_csr_eq_0xc82,114} rvc_constraint;115116typedef enum {117rv_codec_illegal,118rv_codec_none,119rv_codec_u,120rv_codec_uj,121rv_codec_i,122rv_codec_i_sh5,123rv_codec_i_sh6,124rv_codec_i_sh7,125rv_codec_i_csr,126rv_codec_s,127rv_codec_sb,128rv_codec_r,129rv_codec_r_m,130rv_codec_r4_m,131rv_codec_r_a,132rv_codec_r_l,133rv_codec_r_f,134rv_codec_cb,135rv_codec_cb_imm,136rv_codec_cb_sh5,137rv_codec_cb_sh6,138rv_codec_ci,139rv_codec_ci_sh5,140rv_codec_ci_sh6,141rv_codec_ci_16sp,142rv_codec_ci_lwsp,143rv_codec_ci_ldsp,144rv_codec_ci_lqsp,145rv_codec_ci_li,146rv_codec_ci_lui,147rv_codec_ci_none,148rv_codec_ciw_4spn,149rv_codec_cj,150rv_codec_cj_jal,151rv_codec_cl_lw,152rv_codec_cl_ld,153rv_codec_cl_lq,154rv_codec_cr,155rv_codec_cr_mv,156rv_codec_cr_jalr,157rv_codec_cr_jr,158rv_codec_cs,159rv_codec_cs_sw,160rv_codec_cs_sd,161rv_codec_cs_sq,162rv_codec_css_swsp,163rv_codec_css_sdsp,164rv_codec_css_sqsp,165} rv_codec;166167typedef enum {168rv_op_illegal,169rv_op_lui,170rv_op_auipc,171rv_op_jal,172rv_op_jalr,173rv_op_beq,174rv_op_bne,175rv_op_blt,176rv_op_bge,177rv_op_bltu,178rv_op_bgeu,179rv_op_lb,180rv_op_lh,181rv_op_lw,182rv_op_lbu,183rv_op_lhu,184rv_op_sb,185rv_op_sh,186rv_op_sw,187rv_op_addi,188rv_op_slti,189rv_op_sltiu,190rv_op_xori,191rv_op_ori,192rv_op_andi,193rv_op_slli,194rv_op_srli,195rv_op_srai,196rv_op_add,197rv_op_sub,198rv_op_sll,199rv_op_slt,200rv_op_sltu,201rv_op_xor,202rv_op_srl,203rv_op_sra,204rv_op_or,205rv_op_and,206rv_op_fence,207rv_op_fence_i,208rv_op_lwu,209rv_op_ld,210rv_op_sd,211rv_op_addiw,212rv_op_slliw,213rv_op_srliw,214rv_op_sraiw,215rv_op_addw,216rv_op_subw,217rv_op_sllw,218rv_op_srlw,219rv_op_sraw,220rv_op_ldu,221rv_op_lq,222rv_op_sq,223rv_op_addid,224rv_op_sllid,225rv_op_srlid,226rv_op_sraid,227rv_op_addd,228rv_op_subd,229rv_op_slld,230rv_op_srld,231rv_op_srad,232rv_op_mul,233rv_op_mulh,234rv_op_mulhsu,235rv_op_mulhu,236rv_op_div,237rv_op_divu,238rv_op_rem,239rv_op_remu,240rv_op_mulw,241rv_op_divw,242rv_op_divuw,243rv_op_remw,244rv_op_remuw,245rv_op_muld,246rv_op_divd,247rv_op_divud,248rv_op_remd,249rv_op_remud,250rv_op_lr_w,251rv_op_sc_w,252rv_op_amoswap_w,253rv_op_amoadd_w,254rv_op_amoxor_w,255rv_op_amoor_w,256rv_op_amoand_w,257rv_op_amomin_w,258rv_op_amomax_w,259rv_op_amominu_w,260rv_op_amomaxu_w,261rv_op_lr_d,262rv_op_sc_d,263rv_op_amoswap_d,264rv_op_amoadd_d,265rv_op_amoxor_d,266rv_op_amoor_d,267rv_op_amoand_d,268rv_op_amomin_d,269rv_op_amomax_d,270rv_op_amominu_d,271rv_op_amomaxu_d,272rv_op_lr_q,273rv_op_sc_q,274rv_op_amoswap_q,275rv_op_amoadd_q,276rv_op_amoxor_q,277rv_op_amoor_q,278rv_op_amoand_q,279rv_op_amomin_q,280rv_op_amomax_q,281rv_op_amominu_q,282rv_op_amomaxu_q,283rv_op_ecall,284rv_op_ebreak,285rv_op_uret,286rv_op_sret,287rv_op_hret,288rv_op_mret,289rv_op_dret,290rv_op_sfence_vm,291rv_op_sfence_vma,292rv_op_wfi,293rv_op_csrrw,294rv_op_csrrs,295rv_op_csrrc,296rv_op_csrrwi,297rv_op_csrrsi,298rv_op_csrrci,299rv_op_flh,300rv_op_fsh,301rv_op_fmadd_h,302rv_op_fmsub_h,303rv_op_fnmsub_h,304rv_op_fnmadd_h,305rv_op_fadd_h,306rv_op_fsub_h,307rv_op_fmul_h,308rv_op_fdiv_h,309rv_op_fsgnj_h,310rv_op_fsgnjn_h,311rv_op_fsgnjx_h,312rv_op_fmin_h,313rv_op_fmax_h,314rv_op_fsqrt_h,315rv_op_fle_h,316rv_op_flt_h,317rv_op_feq_h,318rv_op_fcvt_w_h,319rv_op_fcvt_wu_h,320rv_op_fcvt_h_w,321rv_op_fcvt_h_wu,322rv_op_fclass_h,323rv_op_fcvt_l_h,324rv_op_fcvt_lu_h,325rv_op_fmv_x_h,326rv_op_fcvt_h_l,327rv_op_fcvt_h_lu,328rv_op_fmv_h_x,329rv_op_fcvt_s_h,330rv_op_fcvt_h_s,331rv_op_fcvt_d_h,332rv_op_fcvt_h_d,333rv_op_fcvt_q_h,334rv_op_fcvt_h_q,335rv_op_fmv_h,336rv_op_fabs_h,337rv_op_fneg_h,338rv_op_flw,339rv_op_fsw,340rv_op_fmadd_s,341rv_op_fmsub_s,342rv_op_fnmsub_s,343rv_op_fnmadd_s,344rv_op_fadd_s,345rv_op_fsub_s,346rv_op_fmul_s,347rv_op_fdiv_s,348rv_op_fsgnj_s,349rv_op_fsgnjn_s,350rv_op_fsgnjx_s,351rv_op_fmin_s,352rv_op_fmax_s,353rv_op_fsqrt_s,354rv_op_fle_s,355rv_op_flt_s,356rv_op_feq_s,357rv_op_fcvt_w_s,358rv_op_fcvt_wu_s,359rv_op_fcvt_s_w,360rv_op_fcvt_s_wu,361rv_op_fmv_x_s,362rv_op_fclass_s,363rv_op_fmv_s_x,364rv_op_fcvt_l_s,365rv_op_fcvt_lu_s,366rv_op_fcvt_s_l,367rv_op_fcvt_s_lu,368rv_op_fld,369rv_op_fsd,370rv_op_fmadd_d,371rv_op_fmsub_d,372rv_op_fnmsub_d,373rv_op_fnmadd_d,374rv_op_fadd_d,375rv_op_fsub_d,376rv_op_fmul_d,377rv_op_fdiv_d,378rv_op_fsgnj_d,379rv_op_fsgnjn_d,380rv_op_fsgnjx_d,381rv_op_fmin_d,382rv_op_fmax_d,383rv_op_fcvt_s_d,384rv_op_fcvt_d_s,385rv_op_fsqrt_d,386rv_op_fle_d,387rv_op_flt_d,388rv_op_feq_d,389rv_op_fcvt_w_d,390rv_op_fcvt_wu_d,391rv_op_fcvt_d_w,392rv_op_fcvt_d_wu,393rv_op_fclass_d,394rv_op_fcvt_l_d,395rv_op_fcvt_lu_d,396rv_op_fmv_x_d,397rv_op_fcvt_d_l,398rv_op_fcvt_d_lu,399rv_op_fmv_d_x,400rv_op_flq,401rv_op_fsq,402rv_op_fmadd_q,403rv_op_fmsub_q,404rv_op_fnmsub_q,405rv_op_fnmadd_q,406rv_op_fadd_q,407rv_op_fsub_q,408rv_op_fmul_q,409rv_op_fdiv_q,410rv_op_fsgnj_q,411rv_op_fsgnjn_q,412rv_op_fsgnjx_q,413rv_op_fmin_q,414rv_op_fmax_q,415rv_op_fcvt_s_q,416rv_op_fcvt_q_s,417rv_op_fcvt_d_q,418rv_op_fcvt_q_d,419rv_op_fsqrt_q,420rv_op_fle_q,421rv_op_flt_q,422rv_op_feq_q,423rv_op_fcvt_w_q,424rv_op_fcvt_wu_q,425rv_op_fcvt_q_w,426rv_op_fcvt_q_wu,427rv_op_fclass_q,428rv_op_fcvt_l_q,429rv_op_fcvt_lu_q,430rv_op_fcvt_q_l,431rv_op_fcvt_q_lu,432rv_op_fmv_x_q,433rv_op_fmv_q_x,434rv_op_c_addi4spn,435rv_op_c_fld,436rv_op_c_lw,437rv_op_c_flw,438rv_op_c_fsd,439rv_op_c_sw,440rv_op_c_fsw,441rv_op_c_nop,442rv_op_c_addi,443rv_op_c_jal,444rv_op_c_li,445rv_op_c_addi16sp,446rv_op_c_lui,447rv_op_c_srli,448rv_op_c_srai,449rv_op_c_andi,450rv_op_c_sub,451rv_op_c_xor,452rv_op_c_or,453rv_op_c_and,454rv_op_c_subw,455rv_op_c_addw,456rv_op_c_j,457rv_op_c_beqz,458rv_op_c_bnez,459rv_op_c_slli,460rv_op_c_fldsp,461rv_op_c_lwsp,462rv_op_c_flwsp,463rv_op_c_jr,464rv_op_c_mv,465rv_op_c_ebreak,466rv_op_c_jalr,467rv_op_c_add,468rv_op_c_fsdsp,469rv_op_c_swsp,470rv_op_c_fswsp,471rv_op_c_ld,472rv_op_c_sd,473rv_op_c_addiw,474rv_op_c_ldsp,475rv_op_c_sdsp,476rv_op_c_lq,477rv_op_c_sq,478rv_op_c_lqsp,479rv_op_c_sqsp,480rv_op_nop,481rv_op_mv,482rv_op_not,483rv_op_neg,484rv_op_negw,485rv_op_sext_w,486rv_op_seqz,487rv_op_snez,488rv_op_sltz,489rv_op_sgtz,490rv_op_fmv_s,491rv_op_fabs_s,492rv_op_fneg_s,493rv_op_fmv_d,494rv_op_fabs_d,495rv_op_fneg_d,496rv_op_fmv_q,497rv_op_fabs_q,498rv_op_fneg_q,499rv_op_beqz,500rv_op_bnez,501rv_op_blez,502rv_op_bgez,503rv_op_bltz,504rv_op_bgtz,505rv_op_ble,506rv_op_bleu,507rv_op_bgt,508rv_op_bgtu,509rv_op_j,510rv_op_ret,511rv_op_jr,512rv_op_rdcycle,513rv_op_rdtime,514rv_op_rdinstret,515rv_op_rdcycleh,516rv_op_rdtimeh,517rv_op_rdinstreth,518rv_op_frcsr,519rv_op_frrm,520rv_op_frflags,521rv_op_fscsr,522rv_op_fsrm,523rv_op_fsflags,524rv_op_fsrmi,525rv_op_fsflagsi,526rv_op_add_uw,527rv_op_andn,528rv_op_bclr,529rv_op_bclri,530rv_op_bext,531rv_op_bexti,532rv_op_binv,533rv_op_binvi,534rv_op_bset,535rv_op_bseti,536rv_op_clmul,537rv_op_clmulh,538rv_op_clmulr,539rv_op_clz,540rv_op_clzw,541rv_op_cpop,542rv_op_cpopw,543rv_op_ctz,544rv_op_ctzw,545rv_op_max,546rv_op_maxu,547rv_op_min,548rv_op_minu,549rv_op_orc_b,550rv_op_orn,551rv_op_rev8,552rv_op_rol,553rv_op_rolw,554rv_op_ror,555rv_op_rori,556rv_op_roriw,557rv_op_rorw,558rv_op_sext_b,559rv_op_sext_h,560rv_op_sh1add,561rv_op_sh1add_uw,562rv_op_sh2add,563rv_op_sh2add_uw,564rv_op_sh3add,565rv_op_sh3add_uw,566rv_op_slli_uw,567rv_op_xnor,568rv_op_zext_h,569} rv_op;570571/* structures */572573typedef struct {574uint64_t pc;575uint64_t inst;576int32_t imm;577uint16_t op;578uint8_t codec;579uint8_t rd;580uint8_t rs1;581uint8_t rs2;582uint8_t rs3;583uint8_t rm;584uint8_t pred;585uint8_t succ;586uint8_t aq;587uint8_t rl;588} rv_decode;589590/* functions */591592size_t riscv_inst_length(rv_inst inst);593void riscv_inst_fetch(const uint8_t *data, rv_inst *instp, size_t *length);594void riscv_disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst);595596#endif597598599